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fixup! coherence: Pack Valid/Dirty SRAM (#36)
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Signed-off-by: Nils Wistoff <[email protected]>
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niwis committed Nov 4, 2024
1 parent 8fc5183 commit 1139c21
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2 changes: 0 additions & 2 deletions core/cache_subsystem/cache_ctrl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -311,8 +311,6 @@ module cache_ctrl
addr_o = mem_req_q.index;
we_o = 1'b1;

be_o.vldrty = hit_way_q;

// set the correct byte enable
be_o.data[cl_offset>>3+:CVA6Cfg.XLEN/8] = mem_req_q.be;
for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++) begin
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