Add sources and config for Cheshire with HPDCache

Bender.yml

@@ -14,6 +14,13 @@ dependencies:
   tech_cells_generic:
     { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
 
+vendor_package:
+  # Vendor in hpdcache RTL so we can include sources in bender manifest
+  - name: hpdcache_vendor
+    target_dir: core/cache_subsystem/hpdcache_vendor
+    upstream: { git: https://github.com/openhwgroup/cv-hpdcache, rev: 019e04f64f4b2d44ff2694d4e8bed0ab152a9885 }
+    include_from_upstream: [ rtl ]
+
 frozen: true
 
 sources:
@@ -57,6 +64,61 @@ sources:
           - core/mmu_sv39x4/cva6_ptw_sv39x4.sv
           - core/cva6_clic_controller.sv
 
+      - target: cv64a6_imafdcsclic_sv39_hpdcache
+        include_dirs:
+          - core/cache_subsystem/hpdcache_vendor/rtl/include
+        files:
+          # HPDCache sources
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_pkg.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_demux.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_sync_buffer.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_fifo_reg.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_fifo_reg_initialized.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_fxarb.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_rrarb.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_mux.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_prio_1hot_encoder.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_sram.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_sram_wbyteenable.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_sram_wmask.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_regbank_wmask_1rw.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_data_downsize.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_data_upsize.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hwpf_stride/hwpf_stride_pkg.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hwpf_stride/hwpf_stride.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hwpf_stride/hwpf_stride_arb.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hwpf_stride/hwpf_stride_snooper.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_amo.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_cmo.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_core_arbiter.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_ctrl.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_ctrl_pe.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_memarray.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_memctrl.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_miss_handler.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_mshr.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_mshr_to_cache_set.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_plru.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_rtab.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_uncached.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_wbuf.sv
+          - core/cache_subsystem/hpdcache_vendor/rtl/src/hpdcache_wbuf_wrapper.sv
+          # CVA6 sources
+          - core/include/cv64a6_imafdcsclic_sv39_hpdcache_config_pkg.sv
+          - core/include/riscv_pkg.sv
+          - core/include/ariane_pkg.sv
+          - core/mmu_sv39/tlb.sv
+          - core/mmu_sv39/mmu.sv
+          - core/mmu_sv39/ptw.sv
+          - core/cva6_accel_first_pass_decoder_stub.sv
+          - core/mmu_sv39x4/cva6_tlb_sv39x4.sv
+          - core/mmu_sv39x4/cva6_mmu_sv39x4.sv
+          - core/mmu_sv39x4/cva6_ptw_sv39x4.sv
+          - core/cva6_clic_controller.sv
+
       - target: cv64a6_imafdc_sv39_wb
         files:
           - core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv

core/cache_subsystem/hpdcache_vendor/rtl/hpdcache.Flist

@@ -0,0 +1,63 @@
+//
+//  Copyright 2023 CEA*
+//  *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA)
+//
+//  SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+//  Licensed under the Solderpad Hardware License v 2.1 (the “License”); you
+//  may not use this file except in compliance with the License, or, at your
+//  option, the Apache License version 2.0. You may obtain a copy of the
+//  License at
+//
+//  https://solderpad.org/licenses/SHL-2.1/
+//
+//  Unless required by applicable law or agreed to in writing, any work
+//  distributed under the License is distributed on an “AS IS” BASIS, WITHOUT
+//  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+//  License for the specific language governing permissions and limitations
+//  under the License.
+//
+//
+//  Authors       : Cesar Fuguet
+//  Creation Date : January, 2023
+//  Description   : File list for the HPDcache
+//  History       :
+//
++incdir+${HPDCACHE_DIR}/rtl/include
+${HPDCACHE_DIR}/rtl/src/hpdcache_pkg.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_demux.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_sync_buffer.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_fifo_reg.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_fifo_reg_initialized.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_fxarb.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_rrarb.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_mux.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_prio_1hot_encoder.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_sram.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_sram_wbyteenable.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_sram_wmask.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_regbank_wmask_1rw.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_data_downsize.sv
+${HPDCACHE_DIR}/rtl/src/common/hpdcache_data_upsize.sv
+${HPDCACHE_DIR}/rtl/src/hwpf_stride/hwpf_stride_pkg.sv
+${HPDCACHE_DIR}/rtl/src/hwpf_stride/hwpf_stride.sv
+${HPDCACHE_DIR}/rtl/src/hwpf_stride/hwpf_stride_arb.sv
+${HPDCACHE_DIR}/rtl/src/hwpf_stride/hwpf_stride_snooper.sv
+${HPDCACHE_DIR}/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_amo.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_cmo.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_core_arbiter.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_ctrl.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_ctrl_pe.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_memarray.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_memctrl.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_miss_handler.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_mshr.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_mshr_to_cache_set.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_plru.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_rtab.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_uncached.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_wbuf.sv
+${HPDCACHE_DIR}/rtl/src/hpdcache_wbuf_wrapper.sv

core/cache_subsystem/hpdcache_vendor/rtl/include/hpdcache_typedef.svh

@@ -0,0 +1,62 @@
+/*
+ *  Copyright 2023 CEA*
+ *  *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA)
+ *
+ *  SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ *  Licensed under the Solderpad Hardware License v 2.1 (the “License”); you
+ *  may not use this file except in compliance with the License, or, at your
+ *  option, the Apache License version 2.0. You may obtain a copy of the
+ *  License at
+ *
+ *  https://solderpad.org/licenses/SHL-2.1/
+ *
+ *  Unless required by applicable law or agreed to in writing, any work
+ *  distributed under the License is distributed on an “AS IS” BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ *  License for the specific language governing permissions and limitations
+ *  under the License.
+ */
+/*
+ *  Authors       : Cesar Fuguet
+ *  Creation Date : February, 2023
+ *  Description   : HPDcache Types' Definition
+ *  History       :
+ */
+`ifndef __HPDCACHE_TYPEDEF_SVH__
+`define __HPDCACHE_TYPEDEF_SVH__
+
+`define HPDCACHE_TYPEDEF_MEM_REQ_T(__name__, addr_t, id_t) \
+    typedef struct packed { \
+        addr_t                                mem_req_addr; \
+        hpdcache_pkg::hpdcache_mem_len_t      mem_req_len; \
+        hpdcache_pkg::hpdcache_mem_size_t     mem_req_size; \
+        id_t                                  mem_req_id; \
+        hpdcache_pkg::hpdcache_mem_command_e  mem_req_command; \
+        hpdcache_pkg::hpdcache_mem_atomic_e   mem_req_atomic; \
+        logic                                 mem_req_cacheable; \
+    } __name__
+
+`define HPDCACHE_TYPEDEF_MEM_RESP_R_T(__name__, id_t, data_t) \
+    typedef struct packed { \
+        hpdcache_pkg::hpdcache_mem_error_e    mem_resp_r_error; \
+        id_t                                  mem_resp_r_id; \
+        data_t                                mem_resp_r_data; \
+        logic                                 mem_resp_r_last; \
+    } __name__
+
+`define HPDCACHE_TYPEDEF_MEM_REQ_W_T(__name__, data_t, be_t) \
+    typedef struct packed { \
+        data_t                                mem_req_w_data; \
+        be_t                                  mem_req_w_be; \
+        logic                                 mem_req_w_last; \
+    } __name__
+
+`define HPDCACHE_TYPEDEF_MEM_RESP_W_T(__name__, id_t) \
+    typedef struct packed { \
+        logic                                 mem_resp_w_is_atomic; \
+        hpdcache_pkg::hpdcache_mem_error_e    mem_resp_w_error; \
+        id_t                                  mem_resp_w_id; \
+    } __name__
+
+`endif

core/cache_subsystem/hpdcache_vendor/rtl/src/common/hpdcache_data_downsize.sv

@@ -0,0 +1,181 @@
+/*
+ *  Copyright 2023 CEA*
+ *  *Commissariat a l'Energie Atomique et aux Energies Alternatives (CEA)
+ *
+ *  SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+ *
+ *  Licensed under the Solderpad Hardware License v 2.1 (the “License”); you
+ *  may not use this file except in compliance with the License, or, at your
+ *  option, the Apache License version 2.0. You may obtain a copy of the
+ *  License at
+ *
+ *  https://solderpad.org/licenses/SHL-2.1/
+ *
+ *  Unless required by applicable law or agreed to in writing, any work
+ *  distributed under the License is distributed on an “AS IS” BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ *  License for the specific language governing permissions and limitations
+ *  under the License.
+ */
+/*
+ *  Authors       : Cesar Fuguet
+ *  Creation Date : November 22, 2022
+ *  Description   : Refill data downsize
+ *  History       :
+ */
+module hpdcache_data_downsize
+//  {{{
+import hpdcache_pkg::*;
+//  Parameters
+//  {{{
+#(
+    parameter int WR_WIDTH = 0,
+    parameter int RD_WIDTH = 0,
+    parameter int DEPTH    = 0,
+
+    localparam type wdata_t = logic [WR_WIDTH-1:0],
+    localparam type rdata_t = logic [RD_WIDTH-1:0]
+)
+//  }}}
+//  Ports
+//  {{{
+(
+    input  logic   clk_i,
+    input  logic   rst_ni,
+
+    input  logic   w_i,
+    output logic   wok_o,
+    input  wdata_t wdata_i,
+
+    input  logic   r_i,
+    output logic   rok_o,
+    output rdata_t rdata_o
+);
+//  }}}
+//  Architecture
+//  {{{
+    //  Local definitions
+    //  {{{
+    localparam int RD_WORDS = WR_WIDTH/RD_WIDTH;
+    localparam int PTR_WIDTH = $clog2(DEPTH);
+    localparam int WORDCNT_WIDTH = $clog2(RD_WORDS);
+    typedef logic [PTR_WIDTH-1:0]  bufptr_t;
+    typedef logic [WORDCNT_WIDTH-1:0]  wordptr_t;
+    typedef logic [PTR_WIDTH:0]  occupancy_t;
+    //  }}}
+
+    //  Internal registers and signals
+    //  {{{
+    rdata_t [DEPTH-1:0][RD_WORDS-1:0]  buf_q;
+    bufptr_t  wrptr_q, wrptr_d;
+    bufptr_t  rdptr_q, rdptr_d;
+    occupancy_t  used_q, used_d;
+    wordptr_t [DEPTH-1:0]  words_q, words_d;
+    logic words_set;
+    logic  full, empty;
+    //  }}}
+
+    //  Control-Path
+    //  {{{
+    assign full = (hpdcache_uint'(used_q) == DEPTH),
+           empty = (used_q == 0),
+           wok_o = ~full,
+           rok_o = ~empty;
+
+    always_comb
+    begin : ctrl_comb
+        automatic logic used_inc, used_dec;
+        automatic logic words_dec;
+
+        rdptr_d = rdptr_q;
+        wrptr_d = wrptr_q;
+        used_dec = 1'b0;
+        used_inc = 1'b0;
+        words_dec = 1'b0;
+        words_set = 1'b0;
+
+        if (w_i && wok_o) begin
+            used_inc  = 1'b1;
+            words_set = 1'b1;
+            if (hpdcache_uint'(wrptr_q) == (DEPTH-1)) begin
+                wrptr_d = 0;
+            end else begin
+                wrptr_d = wrptr_q + 1;
+            end
+        end
+
+        if (r_i && rok_o) begin
+            words_dec = (words_q[rdptr_q] > 0);
+            if (words_q[rdptr_q] == 0) begin
+                used_dec = 1'b1;
+                if (hpdcache_uint'(rdptr_q) == (DEPTH-1)) begin
+                    rdptr_d = 0;
+                end else begin
+                    rdptr_d = rdptr_q + 1;
+                end
+            end
+        end
+
+        case ({used_inc, used_dec})
+            2'b10  : used_d = used_q + 1;
+            2'b01  : used_d = used_q - 1;
+            default: used_d = used_q;
+        endcase
+
+        words_d = words_q;
+        if (words_set) begin
+            words_d[wrptr_q] = wordptr_t'(RD_WORDS - 1);
+        end
+        if (words_dec) begin
+            words_d[rdptr_q] = words_q[rdptr_q] - 1;
+        end
+    end
+
+    always_ff @(posedge clk_i or negedge rst_ni)
+    begin : ctrl_ff
+        if (!rst_ni) begin
+            rdptr_q <= 0;
+            wrptr_q <= 0;
+            used_q <= 0;
+            words_q <= 0;
+        end else begin
+            rdptr_q <= rdptr_d;
+            wrptr_q <= wrptr_d;
+            used_q <= used_d;
+            words_q <= words_d;
+        end
+    end
+    //  }}}
+
+    //  Data-Path
+    //  {{{
+    always_ff @(posedge clk_i or negedge rst_ni)
+    begin : buf_ff
+        if (!rst_ni) begin
+            buf_q <= '0;
+        end else begin
+            if (words_set) begin
+                buf_q[wrptr_q] <= wdata_i;
+            end
+        end
+    end
+
+    assign rdata_o = buf_q[rdptr_q][RD_WORDS - hpdcache_uint'(words_q[rdptr_q]) - 1];
+    //  }}}
+
+    //  Assertions
+    //  {{{
+    //  pragma translate_off
+    initial
+    begin : initial_assertions
+        assert  (DEPTH     >        0)       else $error("DEPTH must be greater than 0");
+        assert  (WR_WIDTH  >        0)       else $error("WR_WIDTH must be greater than 0");
+        assert  (RD_WIDTH  >        0)       else $error("RD_WIDTH must be greater than 0");
+        assert  (RD_WIDTH  < WR_WIDTH)       else $error("RD_WIDTH must be less to WR_WIDTH");
+        assert ((WR_WIDTH  % RD_WIDTH) == 0) else $error("WR_WIDTH must be a multiple RD_WIDTH");
+    end
+    //  pragma translate_on
+    //  }}}
+//  }}}
+endmodule
+//  }}}