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Add fence.t (#14)
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Experimental feature for some security research

Signed-off-by: Nils Wistoff <[email protected]>
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niwis authored and paulsc96 committed Oct 18, 2024
1 parent 0493347 commit 8fad130
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Showing 23 changed files with 398 additions and 30 deletions.
4 changes: 4 additions & 0 deletions core/cache_subsystem/axi_adapter.sv
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ module axi_adapter #(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low

output logic busy_o,
input logic req_i,
input ariane_pkg::ad_req_t type_i,
input ariane_pkg::amo_t amo_i,
Expand Down Expand Up @@ -94,6 +95,9 @@ module axi_adapter #(

assign any_outstanding_aw = outstanding_aw_cnt_q != '0;

// Busy if we're not idle
assign busy_o = state_q != IDLE;

always_comb begin : axi_fsm
// Default assignments
axi_req_o.aw_valid = 1'b0;
Expand Down
10 changes: 5 additions & 5 deletions core/cache_subsystem/cache_ctrl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,9 @@ module cache_ctrl
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic flush_i,
input logic bypass_i, // enable cache
output logic busy_o,
input logic stall_i, // stall new memory requests
// Core request ports
input dcache_req_i_t req_port_i,
output dcache_req_o_t req_port_o,
Expand Down Expand Up @@ -147,7 +147,7 @@ module cache_ctrl

IDLE: begin
// a new request arrived
if (req_port_i.data_req && !flush_i) begin
if (req_port_i.data_req && !stall_i) begin
// request the cache line - we can do this speculatively
req_o = '1;

Expand Down Expand Up @@ -190,15 +190,15 @@ module cache_ctrl
mem_req_d.tag = req_port_i.address_tag;
end
// we speculatively request another transfer
if (req_port_i.data_req && !flush_i) begin
if (req_port_i.data_req && !stall_i) begin
req_o = '1;
end
// ------------
// HIT CASE
// ------------
if (|hit_way_i) begin
// we can request another cache-line if this was a load
if (req_port_i.data_req && !mem_req_q.we && !flush_i) begin
if (req_port_i.data_req && !mem_req_q.we && !stall_i) begin
state_d = WAIT_TAG; // switch back to WAIT_TAG
mem_req_d.index = req_port_i.address_index;
mem_req_d.id = req_port_i.data_id;
Expand Down Expand Up @@ -410,7 +410,7 @@ module cache_ctrl
req_port_o.data_rvalid = ~mem_req_q.killed;
req_port_o.data_rdata = critical_word_i[axi_offset+:CVA6Cfg.XLEN];
// we can make another request
if (req_port_i.data_req && !flush_i) begin
if (req_port_i.data_req && !stall_i) begin
// save index, be and we
mem_req_d.index = req_port_i.address_index;
mem_req_d.id = req_port_i.data_id;
Expand Down
3 changes: 3 additions & 0 deletions core/cache_subsystem/cva6_hpdcache_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -162,6 +162,9 @@ module cva6_hpdcache_subsystem
.flush_i (icache_flush_i),
.en_i (icache_en_i),
.miss_o (icache_miss_o),
.busy_o (),
.stall_i (1'b0),
.init_ni (1'b0),
.areq_i (icache_areq_i),
.areq_o (icache_areq_o),
.dreq_i (icache_dreq_i),
Expand Down
11 changes: 8 additions & 3 deletions core/cache_subsystem/cva6_icache.sv
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,9 @@ module cva6_icache
input logic en_i,
/// to performance counter
output logic miss_o,
output logic busy_o,
input logic stall_i,
input logic init_ni, // do not init after enabling
// address translation requests
input icache_areq_t areq_i,
output icache_arsp_t areq_o,
Expand Down Expand Up @@ -129,6 +132,8 @@ module cva6_icache
} state_e;
state_e state_d, state_q;

assign busy_o = (state_q != IDLE);

///////////////////////////////////////////////////////
// address -> cl_index mapping, interface plumbing
///////////////////////////////////////////////////////
Expand Down Expand Up @@ -192,7 +197,7 @@ module cva6_icache
always_comb begin : p_fsm
// default assignment
state_d = state_q;
cache_en_d = cache_en_q & en_i;// disabling the cache is always possible, enable needs to go via flush
cache_en_d = (cache_en_q | init_ni) & en_i;// disabling the cache is always possible, enable needs to go via flush if we init
flush_en = 1'b0;
cmp_en_d = 1'b0;
cache_rden = 1'b0;
Expand Down Expand Up @@ -236,10 +241,10 @@ module cva6_icache
cmp_en_d = cache_en_q;

// handle pending flushes, or perform cache clear upon enable
if (flush_d || (en_i && !cache_en_q)) begin
if (flush_d || (en_i && !cache_en_q && !init_ni)) begin
state_d = FLUSH;
// wait for incoming requests
end else begin
end else if (!stall_i) begin
// mem requests are for sure invals here
if (!mem_rtrn_vld_i) begin
dreq_o.ready = 1'b1;
Expand Down
6 changes: 6 additions & 0 deletions core/cache_subsystem/cva6_icache_axi_wrapper.sv
Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,9 @@ module cva6_icache_axi_wrapper
input logic flush_i, // flush the icache, flush and kill have to be asserted together
input logic en_i, // enable icache
output logic miss_o, // to performance counter
output logic busy_o,
input logic stall_i,
input logic init_ni,
// address translation requests
input icache_areq_t areq_i,
output icache_arsp_t areq_o,
Expand Down Expand Up @@ -121,6 +124,9 @@ module cva6_icache_axi_wrapper
.flush_i (flush_i),
.en_i (en_i),
.miss_o (miss_o),
.busy_o (busy_o),
.stall_i (stall_i),
.init_ni (init_ni),
.areq_i (areq_i),
.areq_o (areq_o),
.dreq_i (dreq_i),
Expand Down
10 changes: 9 additions & 1 deletion core/cache_subsystem/miss_handler.sv
Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,12 @@ module miss_handler
) (
input logic clk_i,
input logic rst_ni,
output logic busy_o, // miss handler or axi is busy
input logic flush_i, // flush request
output logic flush_ack_o, // acknowledge successful flush
output logic miss_o,
input logic busy_i, // dcache is busy with something
input logic init_ni, // do not init after reset
// Bypass or miss
input logic [NR_PORTS-1:0][$bits(miss_req_t)-1:0] miss_req_i,
// Bypass handling
Expand Down Expand Up @@ -164,6 +166,10 @@ module miss_handler
logic [ 31:0] halfword;
logic [ $clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;

// Busy signals
logic bypass_axi_busy, miss_axi_busy;
assign busy_o = bypass_axi_busy | miss_axi_busy | (state_q != IDLE);

// ------------------------------
// Cache Management
// ------------------------------
Expand Down Expand Up @@ -423,7 +429,7 @@ module miss_handler
be_o.vldrty = '1;
cnt_d = cnt_q + (1'b1 << CVA6Cfg.DCACHE_OFFSET_WIDTH);
// finished initialization
if (cnt_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] == CVA6Cfg.DCACHE_NUM_WORDS - 1)
if (cnt_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:CVA6Cfg.DCACHE_OFFSET_WIDTH] == CVA6Cfg.DCACHE_NUM_WORDS - 1 || init_ni)
state_d = IDLE;
end
// ----------------------
Expand Down Expand Up @@ -610,6 +616,7 @@ module miss_handler
) i_bypass_axi_adapter (
.clk_i(clk_i),
.rst_ni(rst_ni),
.busy_o(bypass_axi_busy),
.req_i(bypass_adapter_req.req),
.type_i(bypass_adapter_req.reqtype),
.amo_i(bypass_adapter_req.amo),
Expand Down Expand Up @@ -645,6 +652,7 @@ module miss_handler
) i_miss_axi_adapter (
.clk_i,
.rst_ni,
.busy_o (miss_axi_busy),
.req_i (req_fsm_miss_valid),
.type_i (req_fsm_miss_req),
.amo_i (AMO_NONE),
Expand Down
14 changes: 14 additions & 0 deletions core/cache_subsystem/std_cache_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,9 @@ module std_cache_subsystem
input logic clk_i,
input logic rst_ni,
input riscv::priv_lvl_t priv_lvl_i,
output logic busy_o,
input logic stall_i, // stall new memory requests
input logic init_ni, // do not init after reset
// I$
input logic icache_en_i, // enable icache (or bypass e.g: in debug mode)
input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together
Expand Down Expand Up @@ -75,6 +78,11 @@ module std_cache_subsystem
axi_req_t axi_req_data;
axi_rsp_t axi_resp_data;

logic icache_busy;
logic dcache_busy;

assign busy_o = icache_busy | dcache_busy;

cva6_icache_axi_wrapper #(
.CVA6Cfg(CVA6Cfg),
.icache_areq_t(icache_areq_t),
Expand All @@ -92,6 +100,9 @@ module std_cache_subsystem
.flush_i (icache_flush_i),
.en_i (icache_en_i),
.miss_o (icache_miss_o),
.busy_o (icache_busy),
.stall_i (stall_i),
.init_ni (init_ni),
.areq_i (icache_areq_i),
.areq_o (icache_areq_o),
.dreq_i (icache_dreq_i),
Expand Down Expand Up @@ -119,6 +130,9 @@ module std_cache_subsystem
.flush_i (dcache_flush_i),
.flush_ack_o (dcache_flush_ack_o),
.miss_o (dcache_miss_o),
.busy_o (dcache_busy),
.stall_i (stall_i),
.init_ni (init_ni),
.axi_bypass_o(axi_req_bypass),
.axi_bypass_i(axi_resp_bypass),
.axi_data_o (axi_req_data),
Expand Down
9 changes: 9 additions & 0 deletions core/cache_subsystem/std_nbdcache.sv
Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,9 @@ module std_nbdcache
input logic flush_i, // high until acknowledged
output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed
output logic miss_o, // we missed on a LD/ST
output logic busy_o,
input logic stall_i, // stall new memory requests
input logic init_ni,
// AMOs
input amo_req_t amo_req_i,
output amo_resp_t amo_resp_o,
Expand Down Expand Up @@ -105,6 +108,10 @@ module std_nbdcache
cache_line_t [ CVA6Cfg.DCACHE_SET_ASSOC-1:0] rdata_ram;
cl_be_t be_ram;

// Busy signals
logic miss_handler_busy;
assign busy_o = |busy | miss_handler_busy;

// ------------------
// Cache Controller
// ------------------
Expand All @@ -119,6 +126,7 @@ module std_nbdcache
) i_cache_ctrl (
.bypass_i (~enable_i),
.busy_o (busy[i]),
.stall_i (stall_i | flush_i),
// from core
.req_port_i(req_ports_i[i]),
.req_port_o(req_ports_o[i]),
Expand Down Expand Up @@ -161,6 +169,7 @@ module std_nbdcache
.cache_line_t(cache_line_t),
.cl_be_t(cl_be_t)
) i_miss_handler (
.busy_o (miss_handler_busy),
.flush_i (flush_i),
.busy_i (|busy),
// AMOs
Expand Down
14 changes: 14 additions & 0 deletions core/cache_subsystem/wt_cache_subsystem.sv
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,9 @@ module wt_cache_subsystem
) (
input logic clk_i,
input logic rst_ni,
output logic busy_o,
input logic stall_i, // stall new memory requests
input logic init_ni,
// I$
input logic icache_en_i, // enable icache (or bypass e.g: in debug mode)
input logic icache_flush_i, // flush the icache, flush and kill have to be asserted together
Expand Down Expand Up @@ -112,6 +115,11 @@ module wt_cache_subsystem
dcache_req_t dcache_adapter;
dcache_rtrn_t adapter_dcache;

logic icache_busy;
logic dcache_busy;

assign busy_o = dcache_busy | icache_busy;

cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg(CVA6Cfg),
Expand All @@ -128,6 +136,9 @@ module wt_cache_subsystem
.flush_i (icache_flush_i),
.en_i (icache_en_i),
.miss_o (icache_miss_o),
.busy_o (icache_busy),
.stall_i (stall_i),
.init_ni (init_ni),
.areq_i (icache_areq_i),
.areq_o (icache_areq_o),
.dreq_i (icache_dreq_i),
Expand Down Expand Up @@ -157,6 +168,9 @@ module wt_cache_subsystem
.clk_i (clk_i),
.rst_ni (rst_ni),
.enable_i (dcache_enable_i),
.busy_o (dcache_busy),
.stall_i (stall_i),
.init_ni (init_ni),
.flush_i (dcache_flush_i),
.flush_ack_o (dcache_flush_ack_o),
.miss_o (dcache_miss_o),
Expand Down
14 changes: 14 additions & 0 deletions core/cache_subsystem/wt_dcache.sv
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,9 @@ module wt_dcache
input logic flush_i, // high until acknowledged
output logic flush_ack_o, // send a single cycle acknowledge signal when the cache is flushed
output logic miss_o, // we missed on a ld/st
output logic busy_o,
input logic stall_i, // stall new memory requests
input logic init_ni,
output logic wbuffer_empty_o,
output logic wbuffer_not_ni_o,

Expand Down Expand Up @@ -124,6 +127,13 @@ module wt_dcache
// wbuffer <-> memory
wbuffer_t [ CVA6Cfg.WtDcacheWbufDepth-1:0] wbuffer_data;

// controllers -> management
logic [ NumPorts-2:0] ctrl_busy;

// missunit -> management
logic missunit_busy;

assign busy_o = |ctrl_busy | missunit_busy | ~wbuffer_empty_o;

///////////////////////////////////////////////////////
// miss handling unit
Expand All @@ -143,8 +153,10 @@ module wt_dcache
.flush_i (flush_i),
.flush_ack_o (flush_ack_o),
.miss_o (miss_o),
.busy_o (missunit_busy),
.wbuffer_empty_i(wbuffer_empty_o),
.cache_en_o (cache_en),
.init_ni (init_ni),
// amo interface
.amo_req_i (amo_req_i),
.amo_resp_o (amo_resp_o),
Expand Down Expand Up @@ -203,6 +215,8 @@ module wt_dcache
.clk_i (clk_i),
.rst_ni (rst_ni),
.cache_en_i (cache_en),
.busy_o (ctrl_busy[k]),
.stall_i (stall_i),
// reqs from core
.req_port_i (req_ports_i[k]),
.req_port_o (req_ports_o[k]),
Expand Down
6 changes: 5 additions & 1 deletion core/cache_subsystem/wt_dcache_ctrl.sv
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,8 @@ module wt_dcache_ctrl
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic cache_en_i,
output logic busy_o,
input logic stall_i, // stall new memory requests
// core request ports
input dcache_req_i_t req_port_i,
output dcache_req_o_t req_port_o,
Expand Down Expand Up @@ -117,6 +119,8 @@ module wt_dcache_ctrl
assign rd_ack_d = rd_ack_i;
assign rd_tag_only_o = '0;

assign busy_o = (state_q != IDLE);

///////////////////////////////////////////////////////
// main control logic
///////////////////////////////////////////////////////
Expand All @@ -135,7 +139,7 @@ module wt_dcache_ctrl
//////////////////////////////////
// wait for an incoming request
IDLE: begin
if (req_port_i.data_req) begin
if (req_port_i.data_req && !stall_i) begin
rd_req_o = 1'b1;
// if read ack then ack the `req_port_o`, and goto `READ` state
if (rd_ack_i) begin
Expand Down
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