Fix bug in WB cache controller

Wait for valid signal from miss handler when killing bypass memory transaction before going to IDLE.
pulp-platform · May 23, 2024 · b58a9bd · b58a9bd
1 parent 4a0ffc5
commit b58a9bd
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/core/cache_subsystem/cache_ctrl.sv b/core/cache_subsystem/cache_ctrl.sv
@@ -536,7 +536,7 @@ module cache_ctrl
 
     if (req_port_i.kill_req) begin
       req_port_o.data_rvalid = 1'b1;
-      if (!(state_q inside {MAKE_UNIQUE, WAIT_REFILL_GNT, WAIT_CRITICAL_WORD})) begin
+      if (!(state_q inside {MAKE_UNIQUE, WAIT_REFILL_GNT, WAIT_REFILL_VALID, WAIT_CRITICAL_WORD})) begin
         state_d = IDLE;
       end
     end