ara: fix parametrization

pulp-platform · Nov 5, 2024 · faa1947 · faa1947
1 parent a101e35
commit faa1947
Show file tree

Hide file tree

Showing 4 changed files with 43 additions and 17 deletions.
diff --git a/core/acc_dispatcher.sv b/core/acc_dispatcher.sv
@@ -23,10 +23,10 @@ module acc_dispatcher
     parameter type exception_t = logic,
     parameter type fu_data_t = logic,
     parameter type scoreboard_entry_t = logic,
-    localparam type accelerator_req_t = acc_pkg::cva6_to_acc_t,
-    parameter type acc_req_t = accelerator_req_t,
-    localparam type accelerator_resp_t = acc_pkg::acc_to_cva6_t,
-    parameter type acc_resp_t = accelerator_resp_t,
+    parameter type acc_req_t = logic,
+    parameter type acc_resp_t = logic,
+    parameter type acc_mmu_req_t  = logic,
+    parameter type acc_mmu_resp_t = logic,
     parameter type acc_cfg_t = logic,
     parameter acc_cfg_t AccCfg = '0
 ) (
@@ -64,8 +64,8 @@ module acc_dispatcher
     input logic acc_no_st_pending_i,
     input dcache_req_i_t [2:0] dcache_req_ports_i,
     // Interface with the MMU
-    output acc_pkg::acc_mmu_req_t acc_mmu_req_o,
-    input acc_pkg::acc_mmu_resp_t acc_mmu_resp_i,
+    output acc_mmu_req_t acc_mmu_req_o,
+    input acc_mmu_resp_t acc_mmu_resp_i,
     // Interface with the controller
     output logic ctrl_halt_o,
     input logic [11:0] csr_addr_i,

diff --git a/core/cva6.sv b/core/cva6.sv
@@ -205,6 +205,22 @@ module cva6
       logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser;
     },
 
+    // Accelerator - CVA6's MMU
+	localparam type acc_mmu_req_t = struct packed {
+      logic                    acc_mmu_misaligned_ex;
+      logic                    acc_mmu_req;
+      logic [CVA6Cfg.VLEN-1:0] acc_mmu_vaddr;
+      logic                    acc_mmu_is_store;
+    },
+
+    localparam type acc_mmu_resp_t = struct packed {
+      logic                    acc_mmu_dtlb_hit;
+      logic [CVA6Cfg.PPNW-1:0] acc_mmu_dtlb_ppn;
+      logic                    acc_mmu_valid;
+      logic [CVA6Cfg.PLEN-1:0] acc_mmu_paddr;
+      exception_t              acc_mmu_exception;
+    },
+
     // AXI types
     parameter type axi_ar_chan_t = struct packed {
       logic [CVA6Cfg.AxiIdWidth-1:0]   id;
@@ -506,8 +522,8 @@ module cva6
   // --------------
   // EX <-> ACC_DISP
   // --------------
-  acc_pkg::acc_mmu_req_t acc_mmu_req;
-  acc_pkg::acc_mmu_resp_t acc_mmu_resp;
+  acc_mmu_req_t acc_mmu_req;
+  acc_mmu_resp_t acc_mmu_resp;
   // --------------
   // ID <-> COMMIT
   // --------------
@@ -936,7 +952,9 @@ module cva6
       .icache_dreq_t(icache_dreq_t),
       .icache_drsp_t(icache_drsp_t),
       .lsu_ctrl_t(lsu_ctrl_t),
-      .x_result_t(x_result_t)
+      .x_result_t(x_result_t),
+      .acc_mmu_req_t(acc_mmu_req_t),
+      .acc_mmu_resp_t(acc_mmu_resp_t)
   ) ex_stage_i (
       .clk_i(clk_i),
       .rst_ni(rst_uarch_n),
@@ -1530,7 +1548,9 @@ module cva6
         .acc_cfg_t         (acc_cfg_t),
         .AccCfg            (AccCfg),
         .acc_req_t         (cvxif_req_t),
-        .acc_resp_t        (cvxif_resp_t)
+        .acc_resp_t        (cvxif_resp_t),
+        .acc_mmu_req_t     (acc_mmu_req_t),
+        .acc_mmu_resp_t    (acc_mmu_resp_t)
     ) i_acc_dispatcher (
         .clk_i                 (clk_i),
         .rst_ni                (rst_ni),

diff --git a/core/ex_stage.sv b/core/ex_stage.sv
@@ -29,7 +29,9 @@ module ex_stage
     parameter type icache_dreq_t = logic,
     parameter type icache_drsp_t = logic,
     parameter type lsu_ctrl_t = logic,
-    parameter type x_result_t = logic
+    parameter type x_result_t = logic,
+    parameter type acc_mmu_req_t  = logic,
+    parameter type acc_mmu_resp_t = logic
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,
@@ -160,8 +162,8 @@ module ex_stage
     // accelerate port result is valid - ACC_DISPATCHER
     input logic acc_valid_i,
     // Accelerator MMU access
-    input acc_pkg::acc_mmu_req_t  acc_mmu_req_i,
-    output acc_pkg::acc_mmu_resp_t acc_mmu_resp_o,
+    input acc_mmu_req_t  acc_mmu_req_i,
+    output acc_mmu_resp_t acc_mmu_resp_o,
     // Enable virtual memory translation - CSR_REGFILE
     input logic enable_translation_i,
     // Enable G-Stage memory translation - CSR_REGFILE
@@ -529,7 +531,9 @@ module ex_stage
       .icache_arsp_t(icache_arsp_t),
       .icache_dreq_t(icache_dreq_t),
       .icache_drsp_t(icache_drsp_t),
-      .lsu_ctrl_t(lsu_ctrl_t)
+      .lsu_ctrl_t(lsu_ctrl_t),
+      .acc_mmu_req_t(acc_mmu_req_t),
+      .acc_mmu_resp_t(acc_mmu_resp_t)
   ) lsu_i (
       .clk_i,
       .rst_ni,

diff --git a/core/load_store_unit.sv b/core/load_store_unit.sv
@@ -25,7 +25,9 @@ module load_store_unit
     parameter type icache_arsp_t = logic,
     parameter type icache_dreq_t = logic,
     parameter type icache_drsp_t = logic,
-    parameter type lsu_ctrl_t = logic
+    parameter type lsu_ctrl_t = logic,
+    parameter type acc_mmu_req_t  = logic,
+    parameter type acc_mmu_resp_t = logic
 ) (
     // Subsystem Clock - SUBSYSTEM
     input logic clk_i,
@@ -83,8 +85,8 @@ module load_store_unit
     input logic en_ld_st_g_translation_i,
 
     // Accelerator request for CVA6's MMU
-    input  acc_pkg::acc_mmu_req_t acc_mmu_req_i,
-    output acc_pkg::acc_mmu_resp_t acc_mmu_resp_o,
+    input  acc_mmu_req_t acc_mmu_req_i,
+    output acc_mmu_resp_t acc_mmu_resp_o,
 
     // Instruction cache input request - CACHES
     input  icache_arsp_t icache_areq_i,