Added Bender.yml file

Bender.yml

@@ -0,0 +1,37 @@
+package:
+  name: hier-icache
+  authors: 
+    - "Jie Chen <[email protected]>"
+    - "Angelo Garofalo <[email protected]>"
+
+dependencies:
+  common_cells: { git: "[email protected]:pulp-platform/common_cells.git", version: 1.13.1 }
+  tech_cells_generic: { git: "[email protected]:pulp-platform/tech_cells_generic", version: 0.1.6 }
+  scm: { git: "[email protected]:pulp-platform/scm.git", version: 1.0.1 }
+  icache-intc: { git: "[email protected]:pulp-platform/icache-intc.git", version: 1.0.1 }
+  axi_slice: { git: "[email protected]:pulp-platform/axi_slice.git", version: 1.1.4 } # deprecated, replaced by axi_cut (in axi repo)
+  axi_node: { git: "[email protected]:pulp-platform/axi_node.git", version: 1.1.4 } # deprecated, replaced by axi_xbar (in axi repo)
+
+sources:
+    # Source files grouped in levels. Files in level 0 have no dependencies on files in this
+    # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
+    # levels 1 and 0, etc. Files within a level are ordered alphabetically.
+    # Level 0
+  - CTRL_UNIT/hier_icache_ctrl_unit.sv
+  - RTL/L1.5_CACHE/ram_ws_rs_data_scm.sv
+  - RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv
+  - RTL/L1.5_CACHE/RefillTracker_4.sv
+  - RTL/L1.5_CACHE/REP_buffer_4.sv
+  - RTL/L1_CACHE/pri_icache_controller.sv
+  - RTL/L1_CACHE/refill_arbiter.sv
+  - RTL/L1_CACHE/register_file_1w_multi_port_read.sv
+    # Level 1
+  - CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv
+  - RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv
+  - RTL/L1.5_CACHE/icache_controller.sv
+  - RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv
+    # Level 2
+  - RTL/L1.5_CACHE/share_icache.sv
+  - RTL/L1_CACHE/pri_icache.sv
+    # Level 3
+  - RTL/TOP/icache_hier_top.sv

src_files.yml

@@ -7,6 +7,7 @@ hier-icache:
     RTL/L1_CACHE/pri_icache_controller.sv,
     RTL/L1_CACHE/refill_arbiter.sv,
     RTL/L1_CACHE/pri_icache.sv,
+    RTL/L1_CACHE/register_file_1w_multi_port_read.sv,
     RTL/L1_CACHE/register_file_1w_multi_port_read_test_wrap.sv,
     RTL/L1.5_CACHE/AXI4_REFILL_Resp_Deserializer.sv,
     RTL/L1.5_CACHE/share_icache.sv,
@@ -17,4 +18,5 @@ hier-icache:
     RTL/L1.5_CACHE/ram_ws_rs_tag_scm.sv,
     CTRL_UNIT/hier_icache_ctrl_unit.sv,
     CTRL_UNIT/hier_icache_ctrl_unit_wrap.sv,
-  ]
+  ]
+