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restore eth_top, tb update
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@chaoqun-liang
chaoqun-liang committed Feb 20, 2024
1 parent e91ed1f commit 94046fc
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Showing 2 changed files with 65 additions and 38 deletions.
73 changes: 36 additions & 37 deletions rtl/eth_top.sv
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// Copyright 2023 ETH Zurich and University of Bologna.
/// Copyright 2023 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
Expand All @@ -11,56 +11,55 @@
`include "register_interface/assign.svh"

module eth_top #(

/// AXI Stream in request struct
parameter type axi_stream_req_t = eth_idma_pkg::axi_stream_req_t,
/// AXI Stream in response struct
parameter type axi_stream_rsp_t = eth_idma_pkg::axi_stream_rsp_t,
/// AXI Stream Data Width
parameter int unsigned DataWidth = 64,
parameter int unsigned DataWidth = 64,
/// AXI Stream Id Width
parameter int unsigned IdWidth = 0,
parameter int unsigned IdWidth = 0,
/// AXI Stream Dest Width = 0
parameter int unsigned DestWidth = 0,
parameter int unsigned DestWidth = 0,
/// AXI Stream User Width
parameter int unsigned UserWidth = 1,
/// Register address width
parameter int unsigned RegAddrWidth = 4,
/// AXI Stream in request struct
parameter type axi_stream_req_t = logic,
/// AXI Stream in response struct
parameter type axi_stream_rsp_t = logic,
parameter int unsigned UserWidth = 1,
/// REGBUS
parameter type reg2hw_itf_t = logic,
parameter type hw2reg_itf_t = logic

//parameter type reg2hw_itf_t = eth_idma_reg_pkg::eth_idma_reg2hw_t,
//parameter type hw2reg_itf_t = eth_idma_reg_pkg::eth_idma_hw2reg_t,
parameter type reg2hw_itf_t = logic,
parameter type hw2reg_itf_t = logic,
parameter int AW_REGBUS = 4
) (
// Internal 125 MHz clock
input wire clk_i ,
input wire rst_ni ,
input wire clk90_int ,
input wire clk_i,
input wire rst_ni,
input wire clk90_int,
// Ethernet: 1000BASE-T RGMII
input wire phy_rx_clk ,
input wire [3:0] phy_rxd ,
input wire phy_rx_ctl ,
output wire phy_tx_clk ,
output wire [3:0] phy_txd ,
output wire phy_tx_ctl ,
output wire phy_reset_n ,
input wire phy_int_n ,
input wire phy_pme_n ,
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
input wire phy_pme_n,
// MDIO
input wire phy_mdio_i ,
output reg phy_mdio_o ,
output reg phy_mdio_oe ,
output wire phy_mdc ,
input wire phy_mdio_i,
output reg phy_mdio_o,
output reg phy_mdio_oe,
output wire phy_mdc,
// AXIS TX/RX
input axi_stream_req_t tx_axis_req_i,
output axi_stream_rsp_t tx_axis_rsp_o,
output axi_stream_req_t rx_axis_req_o,
input axi_stream_rsp_t rx_axis_rsp_i,
input logic idma_req_ready,
input logic idma_rsp_valid,

input logic idma_req_ready,
input logic idma_rsp_valid,
// Reg configs
input reg2hw_itf_t reg2hw_i ,
output hw2reg_itf_t hw2reg_o
input reg2hw_itf_t reg2hw_i,
output hw2reg_itf_t hw2reg_o
);

// ---------------- axis streams for the framing module ----------------------
Expand Down Expand Up @@ -90,7 +89,7 @@ module eth_top #(
.axi_stream_rsp_t ( s_framing_rsp_t ),
.reg2hw_itf_t ( reg2hw_itf_t ),
.hw2reg_itf_t ( hw2reg_itf_t ),
.AW_REGBUS ( RegAddrWidth )
.AW_REGBUS ( AW_REGBUS )
) i_framing_top (
.rst_ni ( rst_ni ),
.clk_i ( clk_i ),
Expand Down
30 changes: 29 additions & 1 deletion target/sim/src/eth_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ module eth_tb

/// timing parameters
localparam time SYS_TCK = 8ns;
localparam time TCK125 = 8ns;
localparam time SYS_TA = 2ns;
localparam time SYS_TT = 6ns;

Expand All @@ -50,6 +51,8 @@ module eth_tb

/// ethernet pads
logic s_clk;
logic s_clk_125MHz_0;
logic s_clk_125MHz_90;
logic s_rst_n;
logic done = 0;
logic error_found = 0;
Expand Down Expand Up @@ -206,7 +209,8 @@ module eth_tb
) i_tx_eth_idma_wrap (
.clk_i ( s_clk ),
.rst_ni ( s_rst_n ),
/// Etherent Internal clocks
.eth_clk_i ( s_clk_125MHz_0 ), // 125MHz in-phase
.eth_clk90_i ( s_clk_125MHz_90 ), // 125 MHz with 90 phase shift
.phy_rx_clk_i ( eth_rxck ),
.phy_rxd_i ( eth_rxd ),
.phy_rx_ctl_i ( eth_rxctl ),
Expand Down Expand Up @@ -249,6 +253,8 @@ module eth_tb
)i_rx_eth_idma_wrap (
.clk_i ( s_clk ),
.rst_ni ( s_rst_n ),
.eth_clk_i ( s_clk_125MHz_0 ), // 125MHz in-phase
.eth_clk90_i ( s_clk_125MHz_90 ), // 125 MHz with 90 phase shift
.phy_rx_clk_i ( eth_txck ),
.phy_rxd_i ( eth_txd ),
.phy_rx_ctl_i ( eth_txctl ),
Expand All @@ -274,6 +280,26 @@ module eth_tb
);

// ------------------------ BEGINNING OF SIMULATION ------------------------

initial begin
while (!done) begin
s_clk_125MHz_0 <= 1;
#(TCK125/2);
s_clk_125MHz_0 <= 0;
#(TCK125/2);
end
end

initial begin
while (!done) begin
s_clk_125MHz_90 <= 0;
#(TCK125/4);
s_clk_125MHz_90 <= 1;
#(TCK125/2);
s_clk_125MHz_90 <= 0;
#(TCK125/4);
end
end

initial begin

Expand All @@ -283,6 +309,8 @@ module eth_tb
$readmemh("../stimuli/rx_mem_init.vmem", i_rx_axi_sim_mem.mem);
$readmemh("../stimuli/eth_frame.vmem", i_tx_axi_sim_mem.mem);



/// TX eth configs
reg_drv_tx.send_write( 'h00, 32'h98001032, 'hf, reg_error); //lower 32bits of MAC address
@(posedge s_clk);
Expand Down

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