Add back VIP

target/sim/vip/get-vips.sh

@@ -37,10 +37,12 @@ else
     echo "The directory ${VIP_DIR} already exists, skipping git clone"
 fi
 echo "Installing i2c eeprom model"
+mkdir -p i2c_eeprom
 cp --verbose "$VIP_DIR"/24FC1025-i2c-eeprom/*.v i2c_eeprom/
 echo "Installing spi flash model"
 mkdir -p spi_flash/S25fs256s
 cp --verbose -r "$VIP_DIR"/S25fs256s-spi-flash/* spi_flash/S25fs256s
 echo "Installing i2s model"
+mkdir -p i2s
 cp --verbose "$VIP_DIR"/24FC1025-i2c-eeprom/24FC1025.v i2s/i2c_if.v
 patch i2s/i2c_if.v < i2s/i2c_if_timings.patch

target/sim/vip/i2c_eeprom/README.md

@@ -0,0 +1,10 @@
+This folder is just a placeholder.
+The verilog model of the Microchip 24FC1025 I2C serial EEPROM is proprietary code of Microchip Technology Inc., distributed under license from Young Engineering. It can currently be downloaded from here: http://ww1.microchip.com/downloads/en/DeviceDoc/24xx1025_Verilog_Model.zip
+
+Once the package has been downloaded, the following steps are necessary to integrate the model in the platform:
+1. unzip it
+2. there is no EULA, but using this file implies implicitly accepting the license agreement
+3. move the newly created files in this directory
+4. uncomment the 24FC1025 section in the `rtl/vip/src_files.yml` file
+5. modify `rtl/tb/tb_pulp.sv` so that the parameter `USE_24FC1025_MODEL` is 1
+6. regenerate the scripts with `generate-scripts` and rebuild the simulation platform

target/sim/vip/i2s/README.md

@@ -0,0 +1,11 @@
+This folder is partially a placeholder; the `i2s` verification IP is incomplete without using part of the I2C model to implement the IC control memory.
+We reuse the verilog model of the Microchip 24FC1025 I2C serial EEPROM that can be downloaded for the `i2c_eeprom` verification IP.
+
+Once the package has been downloaded, the following steps are necessary to integrate the model in the platform:
+1. follow the instructions in `rtl/vip/i2c_eeprom` to download and extract the I2C verification IP.
+2. do `cp ../i2c_eeprom/24FC1025.v i2c_if.v` .
+3. open the newly created `i2c_if.v` file and remove/comment lines from 614 to 671.
+4. do `patch i2c_if.v < i2c_if.patch`
+5. uncomment the I2S section in the `rtl/vip/src_files.yml` file
+6. modify `rtl/tb/tb_pulp.sv` so that the parameter `USE_I2S_MODEL` is 1
+7. regenerate the scripts with `generate-scripts` and rebuild the simulation platform

target/sim/vip/i2s/i2c_if.patch

@@ -0,0 +1,27 @@
+83c83
+< module M24FC1025 (A0, A1, A2, WP, SDA, SCL, RESET);
+---
+> module i2c_if (A0, A1, A2, WP, SDA, SCL, RESET,pdm_ddr,pdm_en,lsb_first,i2s_rst, i2s_mode, i2s_enable,transf_size,i2s_snap_enable);
+95a96,105
+>    output wire pdm_ddr;
+>    output wire pdm_en;
+>    output wire lsb_first;
+>    output wire i2s_rst;
+>    output wire i2s_mode;
+>    output wire i2s_enable;
+>    output wire i2s_snap_enable;
+>    output wire [1:0] transf_size;
+> 
+> 
+471a482,492
+> 
+>    assign pdm_ddr    = MemoryByte_000[0];
+>    assign pdm_en     = MemoryByte_000[1];    
+>    assign lsb_first  = MemoryByte_000[2];
+>    assign i2s_rst         = MemoryByte_000[3];
+>    assign i2s_mode        = MemoryByte_000[4];
+>    assign i2s_enable      = MemoryByte_000[5];
+>    assign transf_size[0]  = MemoryByte_000[6];
+>    assign transf_size[1]  = MemoryByte_000[7];
+>    assign i2s_snap_enable = MemoryByte_001[0];
+>    

target/sim/vip/i2s/i2c_if_timings.patch

@@ -0,0 +1,33 @@
+83c83
+< module M24FC1025 (A0, A1, A2, WP, SDA, SCL, RESET);
+---
+> module i2c_if (A0, A1, A2, WP, SDA, SCL, RESET,pdm_ddr,pdm_en,lsb_first,i2s_rst, i2s_mode, i2s_enable,transf_size,i2s_snap_enable);
+95a96,105
+>    output wire pdm_ddr;
+>    output wire pdm_en;
+>    output wire lsb_first;
+>    output wire i2s_rst;
+>    output wire i2s_mode;
+>    output wire i2s_enable;
+>    output wire i2s_snap_enable;
+>    output wire [1:0] transf_size;
+> 
+> 
+160,161c170,171
+<          tAA = 400;                 // SCL to SDA output delay
+<          tWC = 5000000;             // memory write cycle time
+---
+>          tAA = 100;                 // SCL to SDA output delay
+>          tWC = 100;             // memory write cycle time
+471a482,492
+> 
+>    assign pdm_ddr    = MemoryByte_000[0];
+>    assign pdm_en     = MemoryByte_000[1];    
+>    assign lsb_first  = MemoryByte_000[2];
+>    assign i2s_rst         = MemoryByte_000[3];
+>    assign i2s_mode        = MemoryByte_000[4];
+>    assign i2s_enable      = MemoryByte_000[5];
+>    assign transf_size[0]  = MemoryByte_000[6];
+>    assign transf_size[1]  = MemoryByte_000[7];
+>    assign i2s_snap_enable = MemoryByte_001[0];
+>