Update FPGA flows

pulp-platform · May 16, 2024 · e17fd68 · e17fd68
1 parent 2597c38
commit e17fd68
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Showing 16 changed files with 343 additions and 231 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -222,7 +222,7 @@ fpga_synth_genesys2:
       - target/fpga/pulpissimo-genesys2/reports
       - target/fpga/pulpissimo-genesys2/rtl
       - target/fpga/pulpissimo-genesys2/tcl
-      - target/fpga/pulpissimo-genesys2/pulpissimo_genesys2.xpr
+      - target/fpga/pulpissimo-genesys2/pulpissimo-genesys2.xpr
       - target/fpga/pulpissimo-genesys2/fpga-settings.mk
       - target/fpga/pulpissimo-genesys2/*.log
       - target/fpga/pulpissimo-genesys2/*.cfg
@@ -247,7 +247,7 @@ fpga_synth_nexys_video:
       - target/fpga/pulpissimo-nexys_video/reports
       - target/fpga/pulpissimo-nexys_video/rtl
       - target/fpga/pulpissimo-nexys_video/tcl
-      - target/fpga/pulpissimo-nexys_video/pulpissimo_nexys_video.xpr
+      - target/fpga/pulpissimo-nexys_video/pulpissimo-nexys_video.xpr
       - target/fpga/pulpissimo-nexys_video/fpga-settings.mk
       - target/fpga/pulpissimo-nexys_video/*.log
       - target/fpga/pulpissimo-nexys_video/*.cfg
@@ -272,7 +272,7 @@ fpga_synth_nexys:
       - target/fpga/pulpissimo-nexys/reports
       - target/fpga/pulpissimo-nexys/rtl
       - target/fpga/pulpissimo-nexys/tcl
-      - target/fpga/pulpissimo-nexys/pulpissimo_nexys.xpr
+      - target/fpga/pulpissimo-nexys/pulpissimo-nexys.xpr
       - target/fpga/pulpissimo-nexys/fpga-settings.mk
       - target/fpga/pulpissimo-nexys/*.log
       - target/fpga/pulpissimo-nexys/*.cfg
@@ -297,7 +297,7 @@ fpga_synth_zcu104:
       - target/fpga/pulpissimo-zcu104/reports
       - target/fpga/pulpissimo-zcu104/rtl
       - target/fpga/pulpissimo-zcu104/tcl
-      - target/fpga/pulpissimo-zcu104/pulpissimo_zcu104.xpr
+      - target/fpga/pulpissimo-zcu104/pulpissimo-zcu104.xpr
       - target/fpga/pulpissimo-zcu104/fpga-settings.mk
       - target/fpga/pulpissimo-zcu104/*.log
       - target/fpga/pulpissimo-zcu104/*.cfg
@@ -322,7 +322,7 @@ fpga_synth_zcu102:
       - target/fpga/pulpissimo-zcu102/reports
       - target/fpga/pulpissimo-zcu102/rtl
       - target/fpga/pulpissimo-zcu102/tcl
-      - target/fpga/pulpissimo-zcu102/pulpissimo_zcu102.xpr
+      - target/fpga/pulpissimo-zcu102/pulpissimo-zcu102.xpr
       - target/fpga/pulpissimo-zcu102/fpga-settings.mk
       - target/fpga/pulpissimo-zcu102/*.log
       - target/fpga/pulpissimo-zcu102/*.cfg

diff --git a/target/fpga/pulpissimo-genesys2/constraints/genesys2.xdc b/target/fpga/pulpissimo-genesys2/constraints/genesys2.xdc
@@ -65,6 +65,14 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
+
 #############################################################
 #  _____ ____         _____      _   _   _                  #
 # |_   _/ __ \       / ____|    | | | | (_)                 #

diff --git a/target/fpga/pulpissimo-nexys/constraints/nexys4.xdc b/target/fpga/pulpissimo-nexys/constraints/nexys4.xdc
@@ -76,6 +76,14 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
+
 #############################################################
 #  _____ ____         _____      _   _   _                  #
 # |_   _/ __ \       / ____|    | | | | (_)                 #

diff --git a/target/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc b/target/fpga/pulpissimo-nexys/constraints/nexys4DDR.xdc
@@ -76,6 +76,14 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
+
 #############################################################
 #  _____ ____         _____      _   _   _                  #
 # |_   _/ __ \       / ____|    | | | | (_)                 #

diff --git a/target/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc b/target/fpga/pulpissimo-nexys_video/constraints/nexys_video.xdc
@@ -65,6 +65,14 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
+
 #############################################################
 #  _____ ____         _____      _   _   _                  #
 # |_   _/ __ \       / ____|    | | | | (_)                 #

diff --git a/target/fpga/pulpissimo-vcu108/constraints/vcu108.xdc b/target/fpga/pulpissimo-vcu108/constraints/vcu108.xdc
@@ -64,6 +64,10 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
 # Create asynchronous clock group between slow clock and JTAG TCK.
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]

diff --git a/target/fpga/pulpissimo-zcu102/constraints/zcu102.xdc b/target/fpga/pulpissimo-zcu102/constraints/zcu102.xdc
@@ -65,6 +65,10 @@ set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpis
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
 # Create asynchronous clock group between slow clock and JTAG TCK.
 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
                                -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]

diff --git a/target/fpga/pulpissimo-zcu102/fpga-settings.mk b/target/fpga/pulpissimo-zcu102/fpga-settings.mk
@@ -1,7 +1,7 @@
 export BOARD=zcu102
 export XILINX_PART=xczu9eg-ffvb1156-2-e
 export XILINX_BOARD=xilinx.com:zcu102:part0:3.2
-export FC_CLK_PERIOD_NS=50
+export FC_CLK_PERIOD_NS=62.5
 export PER_CLK_PERIOD_NS=100
 export SLOW_CLK_PERIOD_NS=30517
 $(info Setting environment variables for $(BOARD) board)
diff --git a/target/fpga/pulpissimo-zcu104/constraints/zcu104.xdc b/target/fpga/pulpissimo-zcu104/constraints/zcu104.xdc
@@ -12,17 +12,12 @@
 
 #Create constraint for the clock input of the zcu104 board
 create_clock -period 8.000 -name ref_clk [get_ports ref_clk_p]
-
-#I2S and CAM interface are not used in this FPGA port. Set constraints to
-#disable the clock
-set_case_analysis 0 i_pulpissimo/safe_domain_i/cam_pclk_o
-set_case_analysis 0 i_pulpissimo/safe_domain_i/i2s_slave_sck_o
-#set_input_jitter tck 1.000
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets ref_clk]
 
 ## JTAG
 create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_jtag_tck]
 set_input_jitter tck 1.000
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_pulpissimo/i_padframe/i_pulpissimo_pads/i_all_pads/i_all_pads_pads/i_pad_jtag_tck/O]
 
 
 # minimize routing delay
@@ -34,35 +29,54 @@ set_max_delay -to [get_ports pad_jtag_tdo] 20.000
 set_max_delay -from [get_ports pad_jtag_tms] 20.000
 set_max_delay -from [get_ports pad_jtag_tdi] 20.000
 
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
-set_max_delay -datapath_only -from [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
+set_max_delay -datapath_only -from [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_pulpissimo/i_soc_domain/i_pulp_soc/i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
 
 
 # reset signal
 set_false_path -from [get_ports pad_reset]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_reset_IBUF_inst/O]
 
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_div/i_clk_mux/clk_o]
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_slow_clk_mngr/inst/clk_out1]
+
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out1]
+set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets i_pulpissimo/i_clock_gen/i_clk_manager/inst/clk_out2]
+set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/soc_clk_o]
+set_property CLOCK_DEDICATED_ROUTE TRUE [get_nets i_pulpissimo/i_clock_gen/per_clk_o]
+
 # Set ASYNC_REG attribute for ff synchronizers to place them closer together and
 # increase MTBF
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
-set_property ASYNC_REG true [get_cells i_pulpissimo/soc_domain_i/pulp_soc_i/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim0/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim1/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim2/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_adv_timer/u_tim3/u_in_stage/r_ls_clk_sync_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_apb_timer_unit/s_ref_clk*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/i_ref_clk_sync/i_pulp_sync/r_reg_reg*]
+set_property ASYNC_REG true [get_cells i_pulpissimo/i_soc_domain/i_pulp_soc/soc_peripherals_i/u_evnt_gen/r_ls_sync_reg*]
 
 # Create asynchronous clock group between slow-clk and SoC clock. Those clocks
 # are considered asynchronously and proper synchronization regs are in place
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/safe_domain_i/i_slow_clk_gen/slow_clk_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/i_fpga_clk_gen/soc_clk_o]]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
 
 # Create asynchronous clock group between Per Clock  and SoC clock. Those clocks
 # are considered asynchronously and proper synchronization regs are in place
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_per_o]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
 
 # Create asynchronous clock group between JTAG TCK and SoC clock.
-set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] -group [get_clocks -of_objects [get_pins i_pulpissimo/soc_domain_i/pulp_soc_i/i_clk_rst_gen/clk_soc_o]]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out1]]
+
+# Create asynchronous clock group between JTAG TCK and per clock.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/i_clk_manager/clk_out2]]
+
+# Create asynchronous clock group between slow clock and JTAG TCK.
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins i_pulpissimo/i_clock_gen/slow_clk_o]] \
+                               -group [get_clocks -of_objects [get_pins i_pulpissimo/pad_jtag_tck]]
 
 #############################################################
 #  _____ ____         _____      _   _   _                  #

diff --git a/target/fpga/pulpissimo-zcu104/fpga-settings.mk b/target/fpga/pulpissimo-zcu104/fpga-settings.mk
@@ -1,7 +1,7 @@
 export BOARD=zcu104
 export XILINX_PART=xczu7ev-ffvc1156-2-e
 export XILINX_BOARD=xilinx.com:zcu104:part0:1.1
-export FC_CLK_PERIOD_NS=50
+export FC_CLK_PERIOD_NS=62.5
 export PER_CLK_PERIOD_NS=100
 export SLOW_CLK_PERIOD_NS=30517
 $(info Setting environment variables for $(BOARD) board)