TestBenchGenerator

Documentation: https://stanfordaha.github.io/CGRAFlowDoc/tbg/intro.html

Help

$ python generate_harness.py --help
usage: generate_harness.py [-h] --pnr-io-collateral <collateral_file>.io.json
                           --bitstream <BITSTREAM_FILE>
                           [--trace-file TRACE_FILE]
                           [--max-clock-cycles MAX_CLOCK_CYCLES]
                           [--wrapper-module-name WRAPPER_MODULE_NAME]
                           [--input-chunk-size INPUT_CHUNK_SIZE]
                           [--output-chunk-size OUTPUT_CHUNK_SIZE]
                           [--output-file-name OUTPUT_FILE_NAME] [--use-jtag]
                           [--verify-config] [--trace]
                           [--trace-file-name TRACE_FILE_NAME] [--quiet]

Test the cgra

optional arguments:
  -h, --help            show this help message and exit
  --pnr-io-collateral <collateral_file>.io.json
                        Collateral file generated by SMT-PNR
  --bitstream <BITSTREAM_FILE>
                        Bitstream file containing the CGRA configuration
  --trace-file TRACE_FILE
                        Trace file
  --max-clock-cycles MAX_CLOCK_CYCLES
                        Max number of clock cyles to run
  --wrapper-module-name WRAPPER_MODULE_NAME
                        Name of the wrapper module
  --input-chunk-size INPUT_CHUNK_SIZE
                        Size in bits of the data in the input files
  --output-chunk-size OUTPUT_CHUNK_SIZE
                        Size in bits of the data in the output files
  --output-file-name OUTPUT_FILE_NAME
                        Name of the generated harness file
  --use-jtag            Should this test harness use JTAG to write config
  --verify-config       Should this test harness read back all the config
                        after writing
  --trace               Dump a .vcd using verilator. **NOTE**: If you add the
                        --trace flag, you must use it both with
                        generate_harness.py and verilate.py. Also, you must
                        either use --force-rebuild with verilate.py or be sure
                        to remove any existing verilator binary, e.g. rm -r
                        CGRAGenerator/verilator/generator_z_tb/build/*. One
                        way to do this would be through a make clean rule
  --trace-file-name TRACE_FILE_NAME
  --quiet               Silence cycle counter

$ python verilate.py --help
usage: verilate.py [-h] [--top-module-name TOP_MODULE_NAME]
                   [--harness HARNESS] [--verilog-directory VERILOG_DIRECTORY]
                   [--force-rebuild] [--output-directory OUTPUT_DIRECTORY]
                   [--trace]

Verilator wrapper

optional arguments:
  -h, --help            show this help message and exit
  --top-module-name TOP_MODULE_NAME
                        Top module name
  --harness HARNESS     Path to harness file
  --verilog-directory VERILOG_DIRECTORY
                        Directory containing verilog files to include in the
                        verilator command
  --force-rebuild       Run verilator even if there's an existing binary
  --output-directory OUTPUT_DIRECTORY
                        Directory to place verilator output files
  --trace               Dump a .vcd using verilator. **NOTE**: If you add the
                        --trace flag, you must use it both with
                        generate_harness.py and verilate.py. Also, you must
                        either use --force-rebuild with verilate.py or be sure
                        to remove any existing verilator binary, e.g. rm -r
                        CGRAGenerator/verilator/generator_z_tb/build/*. One
                        way to do this would be through a make clean rule

Example Usage

python generate_harness.py \
    --pnr-io-collateral tests/conv_bw/conv_bw.io.json \
    --bitstream tests/conv_bw/conv_bw_pnr_bitstream \
    --max-clock-cycles 5000000 \
    --output-file-name build/harness.cpp
  
python verilate.py \
    --harness build/harness.cpp \
    --verilog-directory ../CGRAGenerator/hardware/generator_z/top/genesis_verif/ \
    --output-directory build \
    --top-module-name top