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Merge pull request #351 from lsj123lsjlsj/medge-rk3528a-io
feat: add medge-rk3528a io board to the overlays of the rk3528 series
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arch/arm64/boot/dts/rockchip/overlays/medge-rk3528a-io-enable-pcie.dts
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/dts-v1/; | ||
/plugin/; | ||
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#include <dt-bindings/gpio/gpio.h> | ||
#include <dt-bindings/pinctrl/rockchip.h> | ||
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/ { | ||
metadata { | ||
title = "Enable PCIe"; | ||
compatible = "radxa,medge-rk3528a-io"; | ||
category = "misc"; | ||
exclusive = "pcie2x1", "usbdrd_dwc3"; | ||
description = "Enable PCIe. | ||
After enabling PCIe, the USB OTG port is limited to USB 2.0 speed."; | ||
}; | ||
}; | ||
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&{/} { | ||
vcc3v3_pcie: vcc3v3-pcie { | ||
compatible = "regulator-fixed"; | ||
regulator-name = "vcc3v3_pcie"; | ||
regulator-min-microvolt = <3300000>; | ||
regulator-max-microvolt = <3300000>; | ||
startup-delay-us = <5000>; | ||
enable-active-high; | ||
gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; | ||
vin-supply = <&vcc5v0_sys>; | ||
}; | ||
}; | ||
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&pcie_usb_selection { | ||
enable-active-high; | ||
gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; | ||
}; | ||
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&usbdrd_dwc3 { | ||
phys = <&u2phy_otg>; | ||
phy-names = "usb2-phy"; | ||
maximum-speed = "high-speed"; | ||
snps,dis_u2_susphy_quirk; | ||
snps,usb2-lpm-disable; | ||
}; | ||
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&pcie2x1 { | ||
reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; | ||
vpcie3v3-supply = <&vcc3v3_pcie>; | ||
status = "okay"; | ||
}; |
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Original file line number | Diff line number | Diff line change |
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/dts-v1/; | ||
/plugin/; | ||
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/ { | ||
metadata { | ||
title = "Enable PWM4-M1"; | ||
compatible = "radxa,medge-rk3528a-io"; | ||
category = "misc"; | ||
exclusive = "GPIO1_A4"; | ||
description = "Enable PWM4-M1. | ||
On Radxa mEdge-RK3528A IO this is pin 15. | ||
"; | ||
}; | ||
}; | ||
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&pwm4 { | ||
status = "okay"; | ||
pinctrl-names = "active"; | ||
pinctrl-0 = <&pwm4m1_pins>; | ||
}; |
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