target/riscv: set VLENB/MTOPI/MTOPEI existence on 0.11 targets #1207
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commit 5f45b5b ("target/riscv: reg cache entry is initialized before access") introduced an assertion in `riscv_reg_impl_gdb_regno_exist()`. Link: https://github.com/riscv-collab/riscv-openocd/blob/f82c5a7c048eb70fdc4dff6f53002fa1d3a1bda5/src/target/riscv/riscv_reg.c#L385-L389 This assertion fails on RISC-V Debug Spec. 0.11 targets. The commit is intended to fix this. Change-Id: I20b56df1517f4071f4b6e39c83178a29a9cf95b0 Signed-off-by: Evgeniy Naydanov <[email protected]>
aap-sc
approved these changes
Jan 17, 2025
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Ran riscv-tests on the hifive1-reva board we have. These are the results: |
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| int res = riscv_reg_impl_init_cache(target); | ||
| if (res != ERROR_OK) | ||
| return res; |
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Suggested change
| int res = riscv_reg_impl_init_cache(target); | |
| if (res != ERROR_OK) | |
| return res; | |
| // This is a workaround an assert in the regular riscv013 target, the cache is never actually used in the 0.11 target | |
| int res = riscv_reg_impl_init_cache(target); | |
| if (res != ERROR_OK) | |
| return res; |
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| assert(!r->vlenb | ||
| && "VLENB discovery is not supported on RISC-V 0.11 targets"); | ||
| assert(!r->mtopi_readable | ||
| && "MTOPI discovery is not supported on RISC-V 0.11 targets"); | ||
| assert(!r->mtopei_readable | ||
| && "MTOPEI discovery is not supported on RISC-V 0.11 targets"); | ||
| uint32_t non_discoverable_regs[] = { | ||
| GDB_REGNO_VLENB, | ||
| GDB_REGNO_MTOPI, | ||
| GDB_REGNO_MTOPEI | ||
| }; |
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Suggested change
| assert(!r->vlenb | |
| && "VLENB discovery is not supported on RISC-V 0.11 targets"); | |
| assert(!r->mtopi_readable | |
| && "MTOPI discovery is not supported on RISC-V 0.11 targets"); | |
| assert(!r->mtopei_readable | |
| && "MTOPEI discovery is not supported on RISC-V 0.11 targets"); | |
| uint32_t non_discoverable_regs[] = { | |
| GDB_REGNO_VLENB, | |
| GDB_REGNO_MTOPI, | |
| GDB_REGNO_MTOPEI | |
| }; | |
| // riscv_reg_impl_gdb_regno_exist() has an assert on these three registers that their existence is determined elsewhere, in riscv011, they never exist. | |
| assert(!r->vlenb | |
| && "VLENB discovery is not supported on RISC-V 0.11 targets"); | |
| assert(!r->mtopi_readable | |
| && "MTOPI discovery is not supported on RISC-V 0.11 targets"); | |
| assert(!r->mtopei_readable | |
| && "MTOPEI discovery is not supported on RISC-V 0.11 targets"); | |
| uint32_t non_discoverable_regs[] = { | |
| GDB_REGNO_VLENB, | |
| GDB_REGNO_MTOPI, | |
| GDB_REGNO_MTOPEI | |
| }; |
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commit 5f45b5b ("target/riscv: reg cache entry is initialized before access") introduced an assertion in
riscv_reg_impl_gdb_regno_exist().Link:
riscv-openocd/src/target/riscv/riscv_reg.c
Lines 385 to 389 in f82c5a7
Change-Id: I20b56df1517f4071f4b6e39c83178a29a9cf95b0