rename CTRCLEAR to SCTRCLR

SCTRCLR gets VIE instead of IIE in VU-mode

body.adoc

@@ -402,32 +402,32 @@ _Like the <<_transfer_type_filtering, Transfer Type Filtering>> bits in `mctrcon
   {bits: 5,  name: 'rd',    attr: ['5', '0'], type: 2},
   {bits: 3,  name: 'funct3', attr: ['3', '0'], type: 8},
   {bits: 5,  name: 'rs1',   attr: ['5', '0'], type: 4},
-  {bits: 12, name: 'func12', attr: ['12', 'CTRCLEAR (0x104)'], type: 8},
+  {bits: 12, name: 'func12', attr: ['12', 'SCTRCLR (0x104)'], type: 8},
 ]}
 ....
 
-The supervisor CTRCLEAR instruction performs the following operations:
+The SCTRCLR instruction performs the following operations:
 
 * Zeroes all  CTR <<_entry_registers, Entry Registers>>, for all DEPTH values
 * Zeroes the CTR cycle counter and CCV (see <<Cycle Counting>>)
 
-Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows CTRCLEAR, such that it precedes the next qualified control transfer, will return the value 0.  Further, the first recorded transfer following CTRCLEAR will have `ctrdata`.CCV=0. 
+Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next qualified control transfer, will return the value 0.  Further, the first recorded transfer following SCTRCLR will have `ctrdata`.CCV=0. 
 
-CTRCLEAR raises an illegal-instruction exception in U-mode and VU-mode.
+SCTRCLR raises an illegal-instruction exception in U-mode, and a virtual-instruction exception in VU-mode.
 
 == State Enable Access Control
 
-When Smstateen is implemented, the `mstateen0`.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.  When `mstateen0`.CTR=1, accesses to CTR register state behave as described in <<CSRs>> and <<Entry Registers>> above, while CTRCLEAR behaves as described in <<Supervisor CTR Clear Instruction>>.  When `mstateen0`.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception:
+When Smstateen is implemented, the `mstateen0`.CTR bit controls access to CTR register state from privilege modes less privileged than M-mode.  When `mstateen0`.CTR=1, accesses to CTR register state behave as described in <<CSRs>> and <<Entry Registers>> above, while SCTRCLR behaves as described in <<Supervisor CTR Clear Instruction>>.  When `mstateen0`.CTR=0 and the privilege mode is less privileged than M-mode, the following operations raise an illegal-instruction exception:
 
 * Attempts to access `sctrcontrol`, `vsctrcontrol`, or `sctrstatus`
 * Attempts to access `sireg*` when `siselect` is in 0x200..0x2FF, or `vsireg*` when `vsiselect` is in 0x200..0x2FF
-* Execution of the CTRCLEAR instruction
+* Execution of the SCTRCLR instruction
 
 When `mstateen0`.CTR=0, qualified control transfers executed in privilege modes less privileged than M-mode will continue to implicitly update entry registers and `sctrstatus`.
 
 If the H extension is implemented and `mstateen0`.CTR=1, the `hstateen0`.CTR bit controls access to supervisor CTR state (`sctrcontrol`, `sctrstatus`, and `sireg*` when `siselect` is in 0x200..0x2FF) when V=1.  `hstateen0`.CTR is read-only 0 when `mstateen0`.CTR=0.
 
-When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in <<CSRs>> and <<Entry Registers>> above, while CTRCLEAR behaves as described in <<Supervisor CTR Clear Instruction>>.  When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of CTRCLEAR raise a virtual-instruction exception.
+When `mstateen0`.CTR=1 and `hstateen0`.CTR=1, VS-mode accesses to supervisor CTR state behave as described in <<CSRs>> and <<Entry Registers>> above, while SCTRCLR behaves as described in <<Supervisor CTR Clear Instruction>>.  When `mstateen0`.CTR=1 and `hstateen0`.CTR=0, both VS-mode accesses to supervisor CTR state and VS-mode execution of SCTRCLR raise a virtual-instruction exception.
 
 When `hstateen0`.CTR=0, qualified control transfers executed while V=1 will continue to implicitly update entry registers and `sctrstatus`.
 
@@ -593,7 +593,7 @@ else:
 endif
 ----
 
-The CtrCycleCounter is reset on writes to `__x__ctrcontrol`, and on execution of CTRCLEAR, to ensure that any accumulated cycle counts do not persist across a context switch.  
+The CtrCycleCounter is reset on writes to `__x__ctrcontrol`, and on execution of SCTRCLR, to ensure that any accumulated cycle counts do not persist across a context switch.  
 
 An implementation that supports cycle counting must implement CCV and all
 CCM bits, but may implement 0..4 exponent bits in CCE. Unimplemented CCE
@@ -626,7 +626,7 @@ _Though this compressed method of representation results in some imprecision for
 
 The CC value saturates when all implemented bits in CCM and CCE are 1.
 
-The CC value is only valid when the Cycle Count Valid (CCV) bit is set.  If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer.  The next record will have CCV=0 after a write to `__x__ctrcontrol`, or execution of CTRCLEAR, since CtrCycleCounter is reset.  CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter.
+The CC value is only valid when the Cycle Count Valid (CCV) bit is set.  If CCV=0, the CC value might not hold the correct count of elapsed active cycles since the last recorded transfer.  The next record will have CCV=0 after a write to `__x__ctrcontrol`, or execution of SCTRCLR, since CtrCycleCounter is reset.  CCV should additionally be cleared after any other implementation-specific scenarios where active cycles might not be counted in CtrCycleCounter.
 
 === RAS (Return Address Stack) Emulation Mode