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This repository has been archived by the owner on Mar 21, 2024. It is now read-only.

Releases: riscvarchive/riscv-svadu

Release 1.0

30 Nov 19:35
@riscv-tech-admin riscv-tech-admin
v1.0
c1abccf
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Release 1.0 Latest
Latest 
Merge pull request #25 from ved-rivos/ratified

update state to ratified
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Release 1.0-rc2

02 Oct 19:38
@riscv-tech-admin riscv-tech-admin
v1.0-rc2
f441e4c
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Release 1.0-rc2 Pre-release
Pre-release 
Merge pull request #24 from ved-rivos/page_break

add a page break to avoid a single line para
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Release 1.0-rc1

29 Aug 16:28
@ved-rivos ved-rivos
v1.0-rc1
b65e07c
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v1.0-rc1

move to Frozen state
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Release 0.9

29 Aug 15:44
@ved-rivos ved-rivos
v0.9
6fbfd91
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Release 0.9 Pre-release
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v0.9

move to Frozen state
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Release v0.1

29 Sep 00:11
@github-actions github-actions
vv0.1
a9b8c6b
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Updating with assigned bit positions

Signed-off-by: ved-rivos <[email protected]>
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