RISC V 2018 SoftCPU Contest FAQ

FAQ

1. If I have a question not answered by this FAQ, who should I contact?

• Please write to [email protected]

2. Can I use SystemVerilog?

• Your design must simulate in Verilator, you can use any SystemVerilog features found in Verilator.

3. Can I use VHDL?

• Your design must simulate in Verilator. Verilator does not support VHDL.

4. Can I use my HDL language?

• As long as your HDL language generates Verilog that works with Verilator. Please include both:
  • A Makefile to generate your Verilog
  • A copy of the generated Verilog that was used to generate the bitstream.

5. Why are you requiring Verilator?

• The aim is to enable new innovative designs. We want everyone to be able to test and simulate these new designs without having to purchase expensive commercial tools.

6. Does the core have to pass all the compliance suite tests?

• As mentioned in the contest page, it must pass all the RISC-V RV32I compliance tests. Software emulation of less used CPU instructions (by trapping on invalid instructions) is an okay approach.

7. How do I test if my CPU is compatible with the Zephyr demo applications?

• The demo applications to run include:
  • Philosophers
  • Synchronization Need to output messages as provided in the README for those applications.

8. What must I include in my GitHub repository?

• The soft CPU's HDL code
• Constraint and other FPGA-related files necessary to produce a binary bitstream for the respective hardware
• A README with a complete list of instructions and prerequisites, as well as Makefiles or other scripts, needed to produce the bitstream. The README should also include instructions how to simulate the design in Verilator.
• A binary version of the bitstream which can be fully and identically reproduced using the files and instructions mentioned above
• Any necessary Zephyr 1.13 files in the zephyr/ subdirectory (can be a git submodule)

9. What is included in the resource calculate?

• All resources used inside the FPGA (as determined by the bitstream) are included as part of the resource calculation. This includes all peripherals required.

10. How is the "smallest" implementation determined?

• For the "smallest implementation" categories, the smallest number of total resources used is better. Total resources shall include Logic Elements, Math Blocks and internal RAM. In case of a draw, the entry with the higher performance is ranked higher.
• We are working on a more detailed description of the measurement procedure.

11. Is RAM initialization data considered free for the resource usage calculation?

• No.

12. Is there a discussion group for participants to discuss designs?

• Yes, you may join the public discussion group by emailing the address [email protected] using the email you wish to post from. You can view the discussion group posts here.
• If tweeting about the design use the hashtag #RISCVcontest

13. How is performance measured?

• Short answer: we will be measuring performance in absolute DMIPS. We will expand on this point in the coming days.

14. How are the three final winners selected?

• There are 4 categories as listed above. 50, 30 and 10 points will be awarded to any entry that ranks 1st, 2nd and 3rd in each category, respectively (so for example, if a given entry is the 2nd smallest on the Microsemi platform, it will be awarded 30 points). An entry targeting both the Microsemi and Lattice platforms can potentially be awarded points in categories for both vendors, if necessary files and instructions to reproduce are provided for both.

15. Can I use paid tools to synthesize my design?

• No, you are only allowed to use open source or free-of-charge tools so that the results you have obtained can be reproduced by anyone (within reason).

16. Do I need to be physically present at the RISC-V Summit to claim my prize?

• No, you just need to submit before the deadline. Of course, you're encouraged to come to the RISC-V Summit and be there for the announcement of the winners, but we are aware that not all of the contestants can attend.

17. How do I submit an entry?

• Send it via e-mail to [email protected] or submit via the https://riscv-softcpu-contest.org website. Mandatory data include name, surname, email and GitHub repository link.

18. Can I submit more than one entry?

• Yes. Please however provide each entry in a separate repository. If you want, shared code can be provided via a git submodule.

19. Can one entry provide more than one soft CPU?

• No. Please do not put more than one soft CPU in one repository/entry. If you wish to submit more soft CPUs, please submit them as separate entries in separate repos with clear instructions as how to reproduce the particular entry.

20. Do I really need to include a README?

• Most definitely. Judges will need information on how to reproduce your work. The more info you provide the better (within reason). Please provide information on versions of tools used, the platform you were developing on (Linux, Mac, Windows), Makefiles and any other info that’s needed to reproduce your design, otherwise it will be hard to verify. We might contact you on the email you provide and ask for more data if we feel that some info is missing or unclear. If your entry targets both Lattice and Microsemi platforms, please provide separate instructions for each of those. The README should also clarify which bitstream should be programmed to what device.

21. Should my design expose UART pins?

• Yes, we need to be able to verify if it works on real hardware so it has to provide, at minimum, the TX pin.
• Please specify the UART configuration (e.g. baud rate) in the README.