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1. single_cycle single_cycle Public

   My design of the RV32I core, implement on Terasic's DE2 FPGA board.

   SystemVerilog

2. Digital-clock Digital-clock Public

   My design of a digital clock can setting by button. Implement on Terasic's DE2 FPGA.

   SystemVerilog

3. Trafficlights_controller Trafficlights_controller Public

   My assignment of Digital Designs course

4. template template Public

   Latex Template

   TeX

5. fir_filter fir_filter Public

   Design of FIR filter (DSP)

   Verilog