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Use pre-v5 enum names which are now supported by compatibility macros. #4690

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Use pre-v5 enum names which are now supported by compatibility macros. #4690

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b47a74a
Use pre-v5 enum names which are now supported by compatibility macros.
Rot127 Oct 25, 2024
d74ac78
Merge branch 'dev' into capstone-pre-v6-build-fix
XVilka Oct 25, 2024
c681017
Bump CS version to newest next
Rot127 Oct 26, 2024
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2 changes: 1 addition & 1 deletion librz/arch/isa/arm/arm_cs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
Expand Down
36 changes: 18 additions & 18 deletions librz/arch/isa/arm/arm_esil64.c
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Expand Up @@ -15,71 +15,71 @@
#define MEMBASE64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.base))
#define MEMINDEX64(x) rz_str_get_null(cs_reg_name(*handle, insn->detail->arm64.operands[x].mem.index))

RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type) {
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type) {
const char *close_cond[2];
close_cond[0] = "";
close_cond[1] = ",}";
int close_type = 0;
switch (cond_type) {
case ARM64CC_EQ:
case ARM64_CC_EQ:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,?{,");
break;
case ARM64CC_NE:
case ARM64_CC_NE:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,?{,");
break;
case ARM64CC_HS:
case ARM64_CC_HS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,?{,");
break;
case ARM64CC_LO:
case ARM64_CC_LO:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,?{,");
break;
case ARM64CC_MI:
case ARM64_CC_MI:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,?{,");
break;
case ARM64CC_PL:
case ARM64_CC_PL:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,!,?{,");
break;
case ARM64CC_VS:
case ARM64_CC_VS:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,?{,");
break;
case ARM64CC_VC:
case ARM64_CC_VC:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,!,?{,");
break;
case ARM64CC_HI:
case ARM64_CC_HI:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,");
break;
case ARM64CC_LS:
case ARM64_CC_LS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,");
break;
case ARM64CC_GE:
case ARM64_CC_GE:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,");
break;
case ARM64CC_LT:
case ARM64_CC_LT:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,?{,");
break;
case ARM64CC_GT:
case ARM64_CC_GT:
// zf == 0 && nf == vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,");
break;
case ARM64CC_LE:
case ARM64_CC_LE:
// zf == 1 || nf != vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,");
break;
case ARM64CC_AL:
case ARM64_CC_AL:
// always executed
break;
default:
Expand Down Expand Up @@ -129,7 +129,7 @@ static int arm64_reg_width(int reg) {
return 64;
}

static int decode_sign_ext(aarch64_extender extender) {
static int decode_sign_ext(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
case ARM64_EXT_UXTH:
Expand All @@ -153,7 +153,7 @@ static int decode_sign_ext(aarch64_extender extender) {

#define EXT64(x) decode_sign_ext(insn->detail->arm64.operands[x].ext)

static const char *decode_shift_64(aarch64_shifter shift) {
static const char *decode_shift_64(arm64_shifter shift) {
const char *E_OP_SR = ">>";
const char *E_OP_SL = "<<";
const char *E_OP_RR = ">>>";
Expand Down
30 changes: 15 additions & 15 deletions librz/arch/isa/arm/arm_il64.c
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Expand Up @@ -39,35 +39,35 @@ static const char *regs_bound[] = {
* IL for arm64 condition
* unconditional is returned as NULL (rather than true), for simpler code
*/
static RzILOpBool *cond(ARM64CC_CondCode c) {
static RzILOpBool *cond(arm64_cc c) {
switch (c) {
case ARM64CC_EQ:
case ARM64_CC_EQ:
return VARG("zf");
case ARM64CC_NE:
case ARM64_CC_NE:
return INV(VARG("zf"));
case ARM64CC_HS:
case ARM64_CC_HS:
return VARG("cf");
case ARM64CC_LO:
case ARM64_CC_LO:
return INV(VARG("cf"));
case ARM64CC_MI:
case ARM64_CC_MI:
return VARG("nf");
case ARM64CC_PL:
case ARM64_CC_PL:
return INV(VARG("nf"));
case ARM64CC_VS:
case ARM64_CC_VS:
return VARG("vf");
case ARM64CC_VC:
case ARM64_CC_VC:
return INV(VARG("vf"));
case ARM64CC_HI:
case ARM64_CC_HI:
return AND(VARG("cf"), INV(VARG("zf")));
case ARM64CC_LS:
case ARM64_CC_LS:
return OR(INV(VARG("cf")), VARG("zf"));
case ARM64CC_GE:
case ARM64_CC_GE:
return INV(XOR(VARG("nf"), VARG("vf")));
case ARM64CC_LT:
case ARM64_CC_LT:
return XOR(VARG("nf"), VARG("vf"));
case ARM64CC_GT:
case ARM64_CC_GT:
return INV(OR(XOR(VARG("nf"), VARG("vf")), VARG("zf")));
case ARM64CC_LE:
case ARM64_CC_LE:
return OR(XOR(VARG("nf"), VARG("vf")), VARG("zf"));
default:
return NULL;
Expand Down
108 changes: 54 additions & 54 deletions librz/arch/p/analysis/analysis_arm_cs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -187,11 +187,11 @@ static const char *vector_data_type_name(arm_vectordata_type type) {
}
}

static bool cc_holds_cond(ARM64CC_CondCode cc) {
static bool cc_holds_cond(arm64_cc cc) {
#if CS_NEXT_VERSION >= 6
return (cc != ARM64CC_Invalid && cc != ARM64CC_AL && cc != ARM64CC_NV);
#else
return (cc != ARM64CC_INVALID && cc != ARM64CC_AL && cc != ARM64CC_NV);
return (cc != ARM64_CC_INVALID && cc != ARM64_CC_AL && cc != ARM64_CC_NV);
#endif
}

Expand Down Expand Up @@ -344,42 +344,42 @@ static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) {
pj_free(pj);
}

static const char *cc_name64(ARM64CC_CondCode cc) {
static const char *cc_name64(arm64_cc cc) {
switch (cc) {
case ARM64CC_EQ: // Equal
case ARM64_CC_EQ: // Equal
return "eq";
case ARM64CC_NE: // Not equal: Not equal, or unordered
case ARM64_CC_NE: // Not equal: Not equal, or unordered
return "ne";
case ARM64CC_HS: // Unsigned higher or same: >, ==, or unordered
case ARM64_CC_HS: // Unsigned higher or same: >, ==, or unordered
return "hs";
case ARM64CC_LO: // Unsigned lower or same: Less than
case ARM64_CC_LO: // Unsigned lower or same: Less than
return "lo";
case ARM64CC_MI: // Minus, negative: Less than
case ARM64_CC_MI: // Minus, negative: Less than
return "mi";
case ARM64CC_PL: // Plus, positive or zero: >, ==, or unordered
case ARM64_CC_PL: // Plus, positive or zero: >, ==, or unordered
return "pl";
case ARM64CC_VS: // Overflow: Unordered
case ARM64_CC_VS: // Overflow: Unordered
return "vs";
case ARM64CC_VC: // No overflow: Ordered
case ARM64_CC_VC: // No overflow: Ordered
return "vc";
case ARM64CC_HI: // Unsigned higher: Greater than, or unordered
case ARM64_CC_HI: // Unsigned higher: Greater than, or unordered
return "hi";
case ARM64CC_LS: // Unsigned lower or same: Less than or equal
case ARM64_CC_LS: // Unsigned lower or same: Less than or equal
return "ls";
case ARM64CC_GE: // Greater than or equal: Greater than or equal
case ARM64_CC_GE: // Greater than or equal: Greater than or equal
return "ge";
case ARM64CC_LT: // Less than: Less than, or unordered
case ARM64_CC_LT: // Less than: Less than, or unordered
return "lt";
case ARM64CC_GT: // Signed greater than: Greater than
case ARM64_CC_GT: // Signed greater than: Greater than
return "gt";
case ARM64CC_LE: // Signed less than or equal: <, ==, or unordered
case ARM64_CC_LE: // Signed less than or equal: <, ==, or unordered
return "le";
default:
return "";
}
}

static const char *extender_name(aarch64_extender extender) {
static const char *extender_name(arm64_extender extender) {
switch (extender) {
case ARM64_EXT_UXTB:
return "uxtb";
Expand All @@ -402,36 +402,36 @@ static const char *extender_name(aarch64_extender extender) {
}
}

static const char *vas_name(ARM64Layout_VectorLayout vas) {
static const char *vas_name(arm64_vas vas) {
switch (vas) {
case ARM64LAYOUT_VL_8B:
case ARM64_VAS_8B:
return "8b";
case ARM64LAYOUT_VL_16B:
case ARM64_VAS_16B:
return "16b";
case ARM64LAYOUT_VL_4H:
case ARM64_VAS_4H:
return "4h";
case ARM64LAYOUT_VL_8H:
case ARM64_VAS_8H:
return "8h";
case ARM64LAYOUT_VL_2S:
case ARM64_VAS_2S:
return "2s";
case ARM64LAYOUT_VL_4S:
case ARM64_VAS_4S:
return "4s";
case ARM64LAYOUT_VL_2D:
case ARM64_VAS_2D:
return "2d";
case ARM64LAYOUT_VL_1D:
case ARM64_VAS_1D:
return "1d";
case ARM64LAYOUT_VL_1Q:
case ARM64_VAS_1Q:
return "1q";
#if CS_API_MAJOR > 4 && CS_NEXT_VERSION < 6
case ARM64LAYOUT_VL_1B:
case ARM64_VAS_1B:
return "8b";
case ARM64LAYOUT_VL_4B:
case ARM64_VAS_4B:
return "8b";
case ARM64LAYOUT_VL_2H:
case ARM64_VAS_2H:
return "2h";
case ARM64LAYOUT_VL_1H:
case ARM64_VAS_1H:
return "1h";
case ARM64LAYOUT_VL_1S:
case ARM64_VAS_1S:
return "1s";
#endif
default:
Expand Down Expand Up @@ -605,7 +605,7 @@ static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) {
pj_ki(pj, "vector_index", op->vector_index);
}
#if CS_NEXT_VERSION < 6
if (op->vas != ARM64LAYOUT_VL_INVALID)) {
if (op->vas != ARM64_VAS_INVALID) {
#else
if (op->vas != AARCH64LAYOUT_INVALID) {
#endif
Expand Down Expand Up @@ -668,26 +668,26 @@ static int cond_cs2rz_32(int cc) {
}

static int cond_cs2rz_64(int cc) {
if (cc == ARM64CC_AL || cc < 0) {
if (cc == ARM64_CC_AL || cc < 0) {
cc = RZ_TYPE_COND_AL;
} else {
switch (cc) {
case ARM64CC_EQ: cc = RZ_TYPE_COND_EQ; break;
case ARM64CC_NE: cc = RZ_TYPE_COND_NE; break;
case ARM64CC_HS: cc = RZ_TYPE_COND_HS; break;
case ARM64CC_LO: cc = RZ_TYPE_COND_LO; break;
case ARM64CC_MI: cc = RZ_TYPE_COND_MI; break;
case ARM64CC_PL: cc = RZ_TYPE_COND_PL; break;
case ARM64CC_VS: cc = RZ_TYPE_COND_VS; break;
case ARM64CC_VC: cc = RZ_TYPE_COND_VC; break;
case ARM64CC_HI: cc = RZ_TYPE_COND_HI; break;
case ARM64CC_LS: cc = RZ_TYPE_COND_LS; break;
case ARM64CC_GE: cc = RZ_TYPE_COND_GE; break;
case ARM64CC_LT: cc = RZ_TYPE_COND_LT; break;
case ARM64CC_GT: cc = RZ_TYPE_COND_GT; break;
case ARM64CC_LE: cc = RZ_TYPE_COND_LE; break;
case ARM64CC_NV: cc = RZ_TYPE_COND_AL; break;
case ARM64_CC_EQ: cc = RZ_TYPE_COND_EQ; break;
case ARM64_CC_NE: cc = RZ_TYPE_COND_NE; break;
case ARM64_CC_HS: cc = RZ_TYPE_COND_HS; break;
case ARM64_CC_LO: cc = RZ_TYPE_COND_LO; break;
case ARM64_CC_MI: cc = RZ_TYPE_COND_MI; break;
case ARM64_CC_PL: cc = RZ_TYPE_COND_PL; break;
case ARM64_CC_VS: cc = RZ_TYPE_COND_VS; break;
case ARM64_CC_VC: cc = RZ_TYPE_COND_VC; break;
case ARM64_CC_HI: cc = RZ_TYPE_COND_HI; break;
case ARM64_CC_LS: cc = RZ_TYPE_COND_LS; break;
case ARM64_CC_GE: cc = RZ_TYPE_COND_GE; break;
case ARM64_CC_LT: cc = RZ_TYPE_COND_LT; break;
case ARM64_CC_GT: cc = RZ_TYPE_COND_GT; break;
case ARM64_CC_LE: cc = RZ_TYPE_COND_LE; break;
#if CS_NEXT_VERSION >= 6
case ARM64CC_NV: cc = RZ_TYPE_COND_AL; break;
case ARM64CC_Invalid: cc = RZ_TYPE_COND_AL; break;
#endif
}
Expand Down Expand Up @@ -764,10 +764,10 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) {
}

switch (insn->detail->arm64.cc) {
case ARM64CC_GE:
case ARM64CC_GT:
case ARM64CC_LE:
case ARM64CC_LT:
case ARM64_CC_GE:
case ARM64_CC_GT:
case ARM64_CC_LE:
case ARM64_CC_LT:
op->sign = true;
break;
default:
Expand Down
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