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Stabilize Ratified RISC-V Target Features
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As shortly discussed on Zulip
(https://rust-lang.zulipchat.com/#narrow/stream/250483-t-compiler.2Frisc-v/topic/Stabilization.20of.20RISC-V.20Target.20Features/near/394793704), this commit stabilizes the ratified RISC-V instruction bases and extensions.

Specifically, this commit stabilizes the:
* Instruction-Fetch Fence (Zifencei) on v2.0
* Control and Status Register (Zcsr) on v2.0
* Pause Hint (Zihintpause) on v2.0
* Zicntr and Zihpm were ratified March 2023
* Supervisor-level Instructions (S) on v1.12
* Atomic Instructions (A) on v2.0
* Compressed Instructions (C) on v2.0
* Integer Multiplication and Division (M) on v2.0
* Bit Manipulations (B) on v1.0 listed as `zba`, `zbc`, `zbs`
* Scalar Cryptography (Zk) v1.0.1 listed as `zk`, `zkn`, `zknd`, `zkne`, `zknh`, `zkr`, `zks`, `zksed`, `zksh`, `zkt`, `zbkb`, `zbkc` `zkbx`
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@coastalwhite
coastalwhite committed Nov 19, 2023
1 parent e504eff commit d1e69d3
Showing 1 changed file with 59 additions and 70 deletions.
129 changes: 59 additions & 70 deletions crates/std_detect/src/detect/arch/riscv.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -24,26 +24,48 @@ features! {
///
/// The supported ratified RISC-V instruction sets are as follows:
///
/// * RV32E: `"rv32e"`
/// * RV32I: `"rv32i"`
/// * Zifencei: `"zifencei"`
/// * Zihintpause: `"zihintpause"`
/// * RV64I: `"rv64i"`
/// * M: `"m"`
/// * A: `"a"`
/// * Zicsr: `"zicsr"`
/// * Zicntr: `"zicntr"`
/// * Zihpm: `"zihpm"`
/// * F: `"f"`
/// * B: `"b"`
/// * Zba: `"zba"`
/// * Zbb: `"zbb"`
/// * Zbc: `"zbc"`
/// * Zbs: `"zbs"`
/// * C: `"c"`
/// * D: `"d"`
/// * F: `"f"`
/// * M: `"m"`
/// * Q: `"q"`
/// * C: `"c"`
/// * V: `"v"`
/// * Zicntr: `"zicntr"`
/// * Zicsr: `"zicsr"`
/// * Zifencei: `"zifencei"`
/// * Zihintpause: `"zihintpause"`
/// * Zihpm: `"zihpm"`
/// * Zk: `"zk"`
/// * Zbkb: `"zbkb"`
/// * Zbkc: `"zbkc"`
/// * Zbkx: `"zbkx"`
/// * Zkn: `"zkn"`
/// * Zknd: `"zknd"`
/// * Zkne: `"zkne"`
/// * Zknh: `"zknh"`
/// * Zkr: `"zkr"`
/// * Zks: `"zks"`
/// * Zksed: `"zksed"`
/// * Zksh: `"zksh"`
/// * Zkt: `"zkt"`
///
/// There's also bases and extensions marked as standard instruction set,
/// but they are in frozen or draft state. These instruction sets are also
/// reserved by this macro and can be detected in the future platforms.
///
/// Frozen RISC-V instruction sets:
///
/// * Zfh: `"zfh"`
/// * Zfhmin: `"zfhmin"`
/// * Zfinx: `"zfinx"`
/// * Zdinx: `"zdinx"`
/// * Zhinx: `"zhinx"`
Expand All @@ -52,14 +74,9 @@ features! {
///
/// Draft RISC-V instruction sets:
///
/// * RV32E: `"rv32e"`
/// * RV128I: `"rv128i"`
/// * Zfh: `"zfh"`
/// * Zfhmin: `"zfhmin"`
/// * B: `"b"`
/// * J: `"j"`
/// * P: `"p"`
/// * V: `"v"`
/// * Zam: `"zam"`
///
/// Defined by Privileged Specification:
Expand All @@ -70,61 +87,33 @@ features! {
/// * Svinval: `"svinval"`
/// * Hypervisor: `"h"`
///
/// # RISC-V Bit-Manipulation ISA-extensions
///
/// This document defined the following extensions:
///
/// * Zba: `"zba"`
/// * Zbb: `"zbb"`
/// * Zbc: `"zbc"`
/// * Zbs: `"zbs"`
///
/// # RISC-V Cryptography Extensions
///
/// These extensions are defined in Volume I, Scalar & Entropy Source
/// Instructions:
///
/// * Zbkb: `"zbkb"`
/// * Zbkc: `"zbkc"`
/// * Zbkx: `"zbkx"`
/// * Zknd: `"zknd"`
/// * Zkne: `"zkne"`
/// * Zknh: `"zknh"`
/// * Zksed: `"zksed"`
/// * Zksh: `"zksh"`
/// * Zkr: `"zkr"`
/// * Zkn: `"zkn"`
/// * Zks: `"zks"`
/// * Zk: `"zk"`
/// * Zkt: `"zkt"`
///
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
#[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")]
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] rv32i: "rv32i";
/// RV32I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zifencei: "zifencei";
/// "Zifencei" Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zihintpause: "zihintpause";
/// "Zihintpause" Pause Hint
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] rv64i: "rv64i";
/// RV64I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] m: "m";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] m: "m";
/// "M" Standard Extension for Integer Multiplication and Division
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] a: "a";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] a: "a";
/// "A" Standard Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zicsr: "zicsr";
/// "Zicsr", Control and Status Register (CSR) Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zicntr: "zicntr";
/// "Zicntr", Standard Extension for Base Counters and Timers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zihpm: "zihpm";
/// "Zihpm", Standard Extension for Hardware Performance Counters
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
/// "F" Standard Extension for Single-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
/// "D" Standard Extension for Double-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
/// "Q" Standard Extension for Quad-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] c: "c";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] c: "c";
/// "C" Standard Extension for Compressed Instructions

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
Expand All @@ -146,7 +135,7 @@ features! {
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] b: "b";
/// "B" Standard Extension for Bit Manipulation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
/// "J" Standard Extension for Dynamically Translated Languages
Expand All @@ -157,7 +146,7 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
/// "Zam" Standard Extension for Misaligned Atomics

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] s: "s";
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
Expand All @@ -168,39 +157,39 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
/// Hypervisor Extension

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zba: "zba";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zba: "zba";
/// "Zba" Standard Extension for Address Generation Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbb: "zbb";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbb: "zbb";
/// "Zbb" Standard Extension for Basic Bit-Manipulation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbc: "zbc";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbc: "zbc";
/// "Zbc" Standard Extension for Carry-less Multiplication
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbs: "zbs";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbs: "zbs";
/// "Zbs" Standard Extension for Single-Bit instructions

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkb: "zbkb";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkb: "zbkb";
/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkc: "zbkc";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkc: "zbkc";
/// "Zbkc" Standard Extension for Carry-less multiply instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkx: "zbkx";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zbkx: "zbkx";
/// "Zbkx" Standard Extension for Crossbar permutation instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknd: "zknd";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknd: "zknd";
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkne: "zkne";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkne: "zkne";
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknh: "zknh";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zknh: "zknh";
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksed: "zksed";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksed: "zksed";
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksh: "zksh";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zksh: "zksh";
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkr: "zkr";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkr: "zkr";
/// "Zkr" Standard Extension for Entropy Source Extension
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkn: "zkn";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkn: "zkn";
/// "Zkn" Standard Extension for NIST Algorithm Suite
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zks: "zks";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zks: "zks";
/// "Zks" Standard Extension for ShangMi Algorithm Suite
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zk: "zk";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zk: "zk";
/// "Zk" Standard Extension for Standard scalar cryptography extension
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkt: "zkt";
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zkt: "zkt";
/// "Zkt" Standard Extension for Data Independent Execution Latency
}

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