make ALU combinational logic

sh-mug · Nov 28, 2023 · 20ab47f · 20ab47f
1 parent 2e9fbf0
commit 20ab47f
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diff --git a/src/alu.sv b/src/alu.sv
@@ -1,8 +1,6 @@
 `timescale 1ns / 1ps
 
 module alu (
-    input rst_n,
-    input clk,
     input [2:0] inst,
     input [31:0] a,
     input [31:0] b,

diff --git a/test/test_alu.cpp b/test/test_alu.cpp
@@ -7,17 +7,10 @@
 #include <random>
 
 void ValuForTest::exec(const int &_inst, const int &_a, const int &_b) {
-    rst_n = 1;
-    clk = 0;
-
     inst = _inst;
     a = _a;
     b = _b;
     eval();
-
-    // positive edge
-    clk = 1;
-    eval();
 }
 
 class TestAlu : public ::testing::Test {