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Implement missing opcode V_CVT_PK_I16_I32 #2046

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1 change: 1 addition & 0 deletions src/shader_recompiler/frontend/translate/translate.h
Original file line number Diff line number Diff line change
Expand Up @@ -241,6 +241,7 @@ class Translator {
void V_SAD(const GcnInst& inst);
void V_SAD_U32(const GcnInst& inst);
void V_CVT_PK_U16_U32(const GcnInst& inst);
void V_CVT_PK_I16_I32(const GcnInst& inst);
void V_CVT_PK_U8_F32(const GcnInst& inst);
void V_LSHL_B64(const GcnInst& inst);
void V_MUL_F64(const GcnInst& inst);
Expand Down
13 changes: 13 additions & 0 deletions src/shader_recompiler/frontend/translate/vector_alu.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -375,6 +375,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_SAD_U32(inst);
case Opcode::V_CVT_PK_U16_U32:
return V_CVT_PK_U16_U32(inst);
case Opcode::V_CVT_PK_I16_I32:
return V_CVT_PK_I16_I32(inst);
case Opcode::V_CVT_PK_U8_F32:
return V_CVT_PK_U8_F32(inst);
case Opcode::V_LSHL_B64:
Expand Down Expand Up @@ -1182,6 +1184,17 @@ void Translator::V_CVT_PK_U16_U32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.BitFieldInsert(lo, hi, ir.Imm32(16), ir.Imm32(16)));
}

void Translator::V_CVT_PK_I16_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
//Clamp the underflow then clamp the overflow from the result
IR::U32 lo = ir.IMax(src0, ir.Imm32(0x8000), true);
lo = ir.IMin(lo, ir.Imm32(0x7FFF), true);
IR::U32 hi = ir.IMax(src1, ir.Imm32(0x8000), true);
hi = ir.IMin(hi, ir.Imm32(0x7FFF), true);
SetDst(inst.dst[0], ir.BitFieldInsert(lo, hi, ir.Imm32(16), ir.Imm32(16)));
}

void Translator::V_CVT_PK_U8_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
Expand Down
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