appendix draft

tex/figures/chipdev_hack.tex

@@ -3,7 +3,7 @@
     \centering
     \frame{\includegraphics[width=0.9\linewidth]{media/graphics/chipdev_hack.pdf}}
     \caption[
-        Breaking ChipDev's verification flow
+        Error in ChipDev's verification flow
     ]{
         This example shows ChipDev \cite{ChipDev} incorrectly accepting this submission despite a potential mismatch between simulation and synthesis. For example, Verilator will override the \mintinline{systemverilog}{always_comb} with the \mintinline{systemverilog}{assign}, but Yosys will override the \mintinline{systemverilog}{assign} with the \mintinline{systemverilog}{always_comb}. This could be corrected if ChipDev chooses in the future to incorporate a similar verification flow to what is outlined in \autoref{section:complex_tool_setups}.
     }

tex/final/appendix.tex

@@ -1,10 +1,67 @@
-\appendix
 
-\dsp
+\begin{appendices}
 
-\chapter{Appendix Title }{\label{appendix:a}}
-\begin{section}{Section Title}
+\chapter{Open-source Contributions}
+\label{appx:contributions}
 
-Appendicitis
+This appendix identifies several open-source issues and contributions I have made. Most of the contributions in this appendix were related to my efforts as an HDL educator.
 
-\end{section}
+\section{My open-source issues and contributions}
+
+\begin{itemize}
+    \item \url{https://github.com/olofk/fusesoc/pull/645} [\textbf{open-pr}] Improved inheritance elaboration
+    \item \url{https://github.com/verilator/verilator/pull/4409} [\textbf{closed-pr}] Add check for conflicting options e.g. --binary and --lint-only
+    \item \url{https://github.com/olofk/edalize/pull/389} [\textbf{open-pr}] Added support for additional Verilator modes
+    \item \url{https://github.com/Rain92/FPGA-Mandelbrot/pull/1} [\textbf{open-pr}] Fixed build issues
+    \item \url{https://github.com/lowRISC/style-guides/pull/66} [\textbf{closed-pr}] Specified that functions should avoid non-local references
+    \item \url{https://github.com/steveicarus/iverilog/pull/980} [\textbf{closed-pr}] Argumentless functions fix
+    \item \url{https://github.com/verilator/verilator/pull/4172} [\textbf{closed-pr}] Added NEWERSTD warning when using feature in newer language standard
+    \item \url{https://github.com/openhwgroup/cva6/pull/1142} [\textbf{closed-pr}] Improved Acronym List in Glossary
+\end{itemize}
+
+\section{Open-source issues created by my students for my classes}
+
+\begin{itemize}
+    \item \url{https://github.com/YosysHQ/oss-cad-suite-build/issues/28} [\textbf{closed-issue}] nextpnr-gowin support requested
+\end{itemize}
+
+\chapter{Style Guide Survey}
+\label{appx:style_guides}
+
+This appendix identifies several prominent Verilog and SystemVerilog style guides.
+
+\section{Projects that use lowRISC SystemVerilog Coding Style}
+
+\begin{itemize}
+    \item \url{https://github.com/openhwgroup/cva6}
+    \item \url{https://github.com/lowRISC/ibex}
+    \item \url{https://github.com/lowRISC/opentitan}
+    \item \url{https://github.com/openhwgroup/cv32e40p}
+    \item \url{https://github.com/openhwgroup/cvfpu}
+    \item \url{https://github.com/pulp-platform/ara}
+\end{itemize}
+
+\section{Projects that use BSG SystemVerilog Coding Style}
+
+\begin{itemize}
+    \item \url{https://github.com/black-parrot/black-parrot}
+    \item \url{https://github.com/bespoke-silicon-group/basejump_stl}
+\end{itemize}
+
+\section{Misc Style Guides}
+
+\begin{itemize}
+    \item \url{https://michaeltaylor.org/edu/papers/FreescaleVerilog.pdf}
+    \item \url{https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/HDL-Coding-Techniques}
+    \item \url{https://www.intel.com/content/www/us/en/docs/programmable/683082/23-1/recommended-hdl-coding-styles.html}
+    \item \url{https://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/EI/HDLcodingguidelines.PDF?document_id=48203}
+\end{itemize}
+
+\section{Less-complete Style Guides}
+
+\begin{itemize}
+    \item \url{https://github.com/rsd-devel/rsd/wiki/en-devel-coding-convention}
+    \item \url{https://github.com/hughperkins/VeriGPU/blob/main/docs/coding_guidelines.md}
+\end{itemize}
+
+\end{appendices}

tex/thesis.tex

@@ -21,6 +21,7 @@
 \usepackage{placeins}
 \usepackage[all]{hypcap}
 \usepackage{footnote}
+\usepackage[title,titletoc]{appendix}
 
 %---New Definitions and Commands------------------------------------------------------
 \def\p{\partial}
@@ -115,10 +116,11 @@
 \include{chapters/8_other_classes}
 \include{chapters/9_conclusion}
 
+\include{final/appendix}
+
 %=== Final ============================================
 
 \end{mainmatter}
-
 \include{final/references}
 % \include{final/appendix}