improved figures and added ToF

tex/figures/always_ff.tex

@@ -1,7 +1,13 @@
 
 \begin{figure}[t]
     \centering
-    \inputminted[frame=single]{systemverilog}{media/code/always_ff.svh}
-    \caption{Potentially confusing behaviors of \mintinline{systemverilog}{always_ff} blocks}
+    \begin{minipage}{0.75\textwidth}
+        \inputminted{systemverilog}{media/code/always_ff.svh}
+    \end{minipage}
+    \caption[
+        Examples of bug-prone \mintinline{systemverilog}{always_ff} blocks
+    ]{
+        Potentially confusing behaviors of \mintinline{systemverilog}{always_ff} blocks
+    }
     \label{fig:always_ff}
 \end{figure}

tex/figures/asic_flow.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \includegraphics[width=90mm]{media/graphics/asic_flow.jpg}
-    \caption{Abbreviated diagram of ASIC design flow published by Kynix \cite{kynixDesignFlow}}
+    \caption[
+        Abbreviated diagram of ASIC design flow
+    ]{
+        Abbreviated diagram of ASIC design flow published by Kynix \cite{kynixDesignFlow}
+    }
     \label{fig:asic_flow}
 \end{figure}

tex/figures/asicworld.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=\textwidth,height=0.9\textheight,keepaspectratio]{media/graphics/asicworld.pdf}}
-    \caption{This is an example provided by ASIC World that encourages bad design practices \cite{asicworld}}
+    \caption[
+        ASIC World bad example
+    ]{
+        This is an example provided by ASIC World that encourages bad design practices \cite{asicworld}
+    }
     \label{fig:asicworld}
 \end{figure}

tex/figures/c-like.tex

@@ -8,6 +8,7 @@
         \begin{minipage}{0.8\textwidth}
             \footnotesize
             \inputminted[frame=single]{systemverilog}{media/code/c-like/low.svh}
+            \label{subfig:structural_only}
         \end{minipage}
     }
 
@@ -17,10 +18,15 @@
         \begin{minipage}{0.8\textwidth}
             \footnotesize
             \inputminted[frame=single]{systemverilog}{media/code/c-like/high.svh}
+            \label{subfig:c-like_allowed}
         \end{minipage}
     }
 
-    \caption{Comparison of purely structural Verilog versus C-like Verilog. To demonstrate this comparison, provided are two different implementations of the Find First Set operation.}
+    \caption[
+        Structural vs. C-like Verilog
+    ]{
+        Provided is an example of when C-like constructs can be used to write cleaner code compared to purely structural constructs. \autoref{subfig:structural_only} and \autoref{subfig:c-like_allowed} both implement the Find First Set operation.
+    }
     \label{fig:c-like}
 
 \end{figure}

tex/figures/cache_lab.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \inputminted[frame=single]{systemverilog}{media/code/cache_lab/cache.svh}
-    \caption{Snippet of ``Labs with CVA6'' cache lab starter code \cite{labsWithCVA6}}
+    \caption[
+        C-like constructs in ``Labs with CVA6''
+    ]{
+        Snippet of ``Labs with CVA6'''s cache lab starter code \cite{labsWithCVA6}. Uses of \mintinline{systemverilog}{typedef} and \mintinline{systemverilog}{struct} constructs were demonstrated to students.
+    }
     \label{fig:cache_lab}
 \end{figure}

tex/figures/chipdev_hack.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=0.9\linewidth]{media/graphics/chipdev_hack.pdf}}
-    \caption{This example shows ChipDev \cite{ChipDev} incorrectly accepting this submission despite a potential mismatch between simulation and synthesis. For example, Verilator will override the \mintinline{systemverilog}{always_comb} with the \mintinline{systemverilog}{assign}, but Yosys will override the \mintinline{systemverilog}{assign} with the \mintinline{systemverilog}{always_comb}. This could be corrected if ChipDev chooses to incorporate a similar verification flow to what is outlined in \autoref{section:complex_tool_setups}.}
+    \caption[
+        Tricking ChipDev's simulators
+    ]{
+        This example shows ChipDev \cite{ChipDev} incorrectly accepting this submission despite a potential mismatch between simulation and synthesis. For example, Verilator will override the \mintinline{systemverilog}{always_comb} with the \mintinline{systemverilog}{assign}, but Yosys will override the \mintinline{systemverilog}{assign} with the \mintinline{systemverilog}{always_comb}. This could be corrected if ChipDev chooses to incorporate a similar verification flow to what is outlined in \autoref{section:complex_tool_setups}.
+    }
     \label{fig:chipdev_hack}
 \end{figure}

tex/figures/chipdev_questions.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=0.7\linewidth]{media/graphics/chipdev_questions.pdf}}
-    \caption{An example of questions that ChipDev offers. \cite{ChipDev}}
+    \caption[
+        ChipDev's website
+    ]{
+        An example of questions that ChipDev offers. \cite{ChipDev}
+    }
     \label{fig:chipdev_questions}
 \end{figure}

tex/figures/cva6_overview.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=0.9\linewidth]{media/graphics/cva6_overview.pdf}}
-    \caption{CVA6 Block Diagram \cite{cva6}}
+    \caption[
+        CVA6 Block Diagram
+    ]{
+        CVA6 Block Diagram \cite{cva6}
+    }
     \label{fig:cva6_overview}
 \end{figure}

tex/figures/dc_vs_synplify.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \frame{\includegraphics[width=\linewidth]{media/graphics/dc_vs_synplify.pdf}}
-    \caption{Differences in SystemVerilog Support in DC vs. Synplify-Pro from ``Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification'' \cite{sutherland}}
+    \caption[
+        Inconsistencies in SystemVerilog Support in synthesis tools
+    ]{
+        Differences in SystemVerilog Support in Synopsys Design Compiler vs. Synopsys Synplify-Pro from ``Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification'' \cite{sutherland}
+    }
     \label{fig:dc_vs_synplify}
 \end{figure}

tex/figures/digitaljs_online.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \includegraphics[width=\linewidth]{media/graphics/digitaljs_online.pdf}
-    \caption{Schematic for a Parallel-in Serial-out shift register generated by the netlist graph viewer DigitalJS Online \cite{DigitalJSOnline}}
+    \caption[
+        DigitalJS Online Example
+    ]{
+        Schematic for a Parallel-in Serial-out shift register generated by the netlist graph viewer DigitalJS Online \cite{DigitalJSOnline}
+    }
     \label{fig:digitaljs_online}
 \end{figure}

tex/figures/ece152a_pkg.tex

@@ -3,6 +3,10 @@
     \centering
     \small
     \inputminted[frame=single]{systemverilog}{media/code/ece152a_pkg.sv}
-    \caption{This is a SystemVerilog package that was provided to ECE 152A students to aid in their implementation of a 1965 Ford Thunderbird taillight state-machine.}
+    \caption[
+        \mintinline{systemverilog}{package} included in introductory SystemVerilog course
+    ]{
+        This is a SystemVerilog \mintinline{systemverilog}{package} that was provided to ECE 152A students to aid in their implementation of a 1965 Ford Thunderbird taillight state-machine.
+    }
     \label{fig:ece152a_pkg}
 \end{figure}

tex/figures/opt.tex

@@ -3,32 +3,36 @@
     \centering
 
     \subfloat[
-        If any bits of \mintinline{systemverilog}{a} are set, then \mintinline{systemverilog}{out} is \mintinline{systemverilog}{1}.
+        Superfluous implementation of \mintinline{systemverilog}{assign out = |a;}
     ]{
-        \begin{minipage}{0.8\textwidth}
+        \begin{minipage}{0.55\textwidth}
             \inputminted[frame=single]{systemverilog}{media/code/opt.svh}
         \end{minipage}
     }
 
     \subfloat[
-        Vivado infers the code as one parallel LUT.
+        Vivado correctly infers the code into one parallel LUT.
     ]{
         \includegraphics[width=0.9\linewidth]{media/graphics/opt/vivado.pdf}
     }
 
     \subfloat[
-        Yosys without optimizations enabled infers the code as a series of 2:1 MUXes.
+        Yosys without optimizations enabled inefficiently infers the code as a series of 2:1 MUXes.
     ]{
         \includegraphics[width=0.7\linewidth]{media/graphics/opt/yosys_noopt.pdf}
     }
 
     \subfloat[
-        Yosys with optimizations enabled infers the code as one parallel OR gate.
+        Yosys with optimizations enabled corrects the inference into one parallel OR gate.
     ]{
         \includegraphics[width=0.7\linewidth]{media/graphics/opt/yosys_opt.pdf}
     }
 
-    \caption{Comparison of differences in synthesis.}
+    \caption[
+        Comparison of synthesis optimizations
+    ]{
+        Comparison of synthesis optimizations
+    }
     \label{fig:opt}
 
 \end{figure}

tex/figures/unreadable_opt.tex

@@ -2,6 +2,10 @@
 \begin{figure}[t]
     \centering
     \inputminted[frame=single]{systemverilog}{media/code/unreadable_opt.svh}
-    \caption{Student drastically reduced readability and transferability in order to save 1 logic cell over the teacher solution.}
+    \caption[
+        Code optimized at expense of readability
+    ]{
+        A ECE 152A student drastically reduced their code's readability and transferability in order to save 1 logic cell over the teacher solution.
+    }
     \label{fig:unreadable_opt}
 \end{figure}

tex/thesis.tex

@@ -3,7 +3,7 @@
 \pdfoutput=1
 
 %--- Packages ---------------------------------------------------------
-\usepackage[lofdepth,lotdepth,caption=false]{subfig}
+\usepackage[lotdepth,caption=false]{subfig}
 \usepackage{fancyhdr}
 \usepackage[hyphens]{url}
 % \usepackage{hyperref}
@@ -19,6 +19,7 @@
 \usepackage{siunitx}
 \usepackage{doi}
 \usepackage{placeins}
+\usepackage[all]{hypcap}
 
 %---New Definitions and Commands------------------------------------------------------
 \def\p{\partial}
@@ -44,6 +45,8 @@
 \renewcommand{\chapterautorefname}{Chapter}
 \renewcommand{\sectionautorefname}{Section}
 \renewcommand{\contentsname}{Table of Contents}
+\renewcommand{\bibname}{References}
+\newcommand{\subfigureautorefname}{Subfigure}
 
 %---Set Margins ------------------------------------------------------
 \setlength\oddsidemargin{0.25 in} \setlength\evensidemargin{0.25 in} \setlength\textwidth{6.25 in} \setlength\textheight{8.50 in}
@@ -62,10 +65,10 @@
 	\maketitle
 	\approvalpage
 	\copyrightpage
-	% \input{preliminary/vitae}
 	\input{preliminary/abstract}
 	\tableofcontents
   \addtocontents{toc}{\protect{\pdfbookmark[0]{\contentsname}{toc}}}
+  \listoffigures
 \end{frontmatter}
 
 \begin{mainmatter}
@@ -112,11 +115,9 @@
 
 %=== Final ============================================
 
-% \include{final/appendix}
-% \include{final/glossary}
-
 \end{mainmatter}
 
 \include{final/references}
+% \include{final/appendix}
 
 \end{document}