added gls files

media/code/asicworld/Makefile

@@ -0,0 +1,25 @@
+
+all: clean icarus verilator
+
+SRCS := bad.vh good.vh serial_crc.v
+VLT := --trace-fst --trace-structs --x-assign unique --x-initial unique --binary -Wno-fatal --top tb
+
+lint:
+	verilator tb.sv test.sv --lint-only --timing
+
+obj_dir/Vtb: ${SRCS} build/synth.v tb.sv
+	verilator tb.sv synth/ice40.v build/synth.v test.v serial_crc.v ${VLT} -DGLS -DNO_ICE40_DEFAULT_ASSIGNMENTS
+verilator: obj_dir/Vtb
+	./obj_dir/Vtb +verilator+rand+reset+2
+
+Vtb.vvp: ${SRCS} build/synth.v tb.sv
+	iverilog tb.sv synth/ice40.v build/synth.v test.v serial_crc.v -g2012 -o $@
+icarus: Vtb.vvp
+	./Vtb.vvp -fst
+
+build/synth.v: ${SRCS} synth/yosys.tcl
+	mkdir -p build
+	cd build && yosys -l yosys.log -p 'tcl ../synth/yosys.tcl' && sed -i '0,/module test/s//module synth/' synth.v
+
+clean:
+	rm -rf obj_dir Vtb.vvp build

media/code/asicworld/bad.vh

@@ -0,0 +1,26 @@
+
+always @ (posedge clk)
+if (reset) begin
+  lfsr <= 16'hFFFF;
+end else if (enable) begin
+  if (init) begin
+    lfsr <=  16'hFFFF;
+  end else begin
+    lfsr[0]  <= data_in ^ lfsr[15];
+    lfsr[1]  <= lfsr[0];
+    lfsr[2]  <= lfsr[1];
+    lfsr[3]  <= lfsr[2];
+    lfsr[4]  <= lfsr[3];
+    lfsr[5]  <= lfsr[4] ^ data_in ^ lfsr[15];
+    lfsr[6]  <= lfsr[5];
+    lfsr[7]  <= lfsr[6];
+    lfsr[8]  <= lfsr[7];
+    lfsr[9]  <= lfsr[8];
+    lfsr[10] <= lfsr[9];
+    lfsr[11] <= lfsr[10];
+    lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
+    lfsr[13] <= lfsr[12];
+    lfsr[14] <= lfsr[13];
+    lfsr[15] <= lfsr[14];
+  end
+end

media/code/asicworld/good.vh

@@ -0,0 +1,35 @@
+
+reg [15:0] lfsr_d, lfsr_q;
+
+always @* begin
+  if (init) begin
+    lfsr_d =  16'hFFFF;
+  end else begin
+    lfsr_d[0]  = data_in ^ lfsr_q[15];
+    lfsr_d[1]  = lfsr_q[0];
+    lfsr_d[2]  = lfsr_q[1];
+    lfsr_d[3]  = lfsr_q[2];
+    lfsr_d[4]  = lfsr_q[3];
+    lfsr_d[5]  = lfsr_q[4] ^ data_in ^ lfsr_q[15];
+    lfsr_d[6]  = lfsr_q[5];
+    lfsr_d[7]  = lfsr_q[6];
+    lfsr_d[8]  = lfsr_q[7];
+    lfsr_d[9]  = lfsr_q[8];
+    lfsr_d[10] = lfsr_q[9];
+    lfsr_d[11] = lfsr_q[10];
+    lfsr_d[12] = lfsr_q[11] ^ data_in ^ lfsr_q[15];
+    lfsr_d[13] = lfsr_q[12];
+    lfsr_d[14] = lfsr_q[13];
+    lfsr_d[15] = lfsr_q[14];
+  end
+end
+
+always @(posedge clk) begin
+  if (reset) begin
+    lfsr_q <= 16'hffff;
+  end else if (enable) begin
+    lfsr_q <= lfsr_d;
+  end
+end
+
+always @* lfsr = lfsr_q;

media/code/asicworld/serial_crc.v

@@ -0,0 +1,43 @@
+//-----------------------------------------------------
+// Design Name : serial_crc_ccitt
+// File Name   : serial_crc.v
+// Function    : CCITT Serial CRC
+// Coder       : Deepak Kumar Tala
+//-----------------------------------------------------
+module serial_crc_ccitt #(
+    parameter IMPLEMENTATION = 2
+) (
+clk     ,
+reset   ,
+enable  ,
+init    ,
+data_in ,
+crc_out
+);
+//-----------Input Ports---------------
+input clk     ;
+input reset   ;
+input enable  ;
+input init    ;
+input data_in ;
+//-----------Output Ports---------------
+output [15:0] crc_out;
+//------------Internal Variables--------
+reg   [15:0] lfsr;
+//-------------Code Start-----------------
+assign crc_out = lfsr;
+// Logic to CRC Calculation
+generate if (IMPLEMENTATION == 0) begin : bad
+    `include "bad.vh"
+end else if (IMPLEMENTATION == 1) begin : good
+    `include "good.vh"
+end else begin
+    `ifndef SYNTHESIS
+        initial begin
+            $display("ERROR: Expected valid values for IMPLEMENTATION are 0 for \"bad.vh\" or 1 for \"good.vh\". Received \"%d\".", IMPLEMENTATION);
+            $finish;
+        end
+    `endif
+end endgenerate
+
+endmodule