Refactoring

lambdalib/stdlib/rtl/la_dsync.v

@@ -9,25 +9,25 @@ module la_dsync #(parameter PROP = "DEFAULT",
                   parameter RND = 1)          // randomize simulation delay
    (
     input  clk, // clock
-    input  in,  // input data
+    input  in, // input data
     output out  // synchronized data
     );
 
-    reg     [STAGES:0] shiftreg;
-    integer            sync_delay;
+   reg [STAGES:0] shiftreg;
+   integer        sync_delay;
 
-    always @(posedge clk) begin
-        shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
+   always @(posedge clk) begin
+      shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
 `ifdef SIMULATION
-        sync_delay <= {$random} % 2;
+      sync_delay <= {$random} % 2;
 `endif
-    end
+   end
 
 `ifdef SIMULATION
    assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1];
 
 `else
-    assign out = shiftreg[STAGES-1];
+   assign out = shiftreg[STAGES-1];
 `endif
 
 endmodule

lambdalib/stdlib/rtl/la_rsync.v

@@ -17,17 +17,18 @@ module la_rsync #(parameter PROP = "DEFAULT",
    reg     [STAGES:0] sync_pipe;
    integer            sync_delay;
 
-`ifdef SIMULATION
-    always @(posedge clk) sync_delay <= {$random} % 2;
-`endif
 
    always @(posedge clk or negedge nrst_in)
-     if (!nrst_in) sync_pipe[STAGES:0] <= 'b0;
-     else sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
+     if (!nrst_in)
+       sync_pipe[STAGES:0] <= 'b0;
+     else
+       sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
 
 `ifdef SIMULATION
-   assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1];
+   always @(posedge clk)
+     sync_delay <= {$random} % 2;
 
+   assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1];
 `else
    assign nrst_out = sync_pipe[STAGES-1];
 `endif