Fixing linting/formatting error

siliconcompiler · May 4, 2024 · 453186e · 453186e
1 parent e1f0f4a
commit 453186e
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Showing 2 changed files with 22 additions and 21 deletions.
diff --git a/lambdalib/stdlib/rtl/la_dsync.v b/lambdalib/stdlib/rtl/la_dsync.v
@@ -5,30 +5,31 @@
 //#############################################################################
 
 module la_dsync #(
-    parameter PROP = "DEFAULT"
-) (
-    input  clk,  // clock
-    input  in,   // input data
+                  parameter PROP = "DEFAULT"
+                  )
+   (
+    input  clk, // clock
+    input  in, // input data
     output out   // synchronized data
-);
+    );
 
-    localparam STAGES = 2;
-    localparam RND = 1;
+   localparam STAGES = 2;
+   localparam RND = 1;
 
-    reg     [STAGES:0] shiftreg;
-    integer            sync_delay;
+   reg [STAGES:0] shiftreg;
+   integer        sync_delay;
 
-    always @(posedge clk) begin
-        shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
+   always @(posedge clk) begin
+      shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
 `ifndef SYNTHESIS
-        sync_delay <= {$random} % 2;
+      sync_delay <= {$random} % 2;
 `endif
-    end
+   end
 
 `ifdef SYNTHESIS
-    assign out = shiftreg[STAGES-1];
+   assign out = shiftreg[STAGES-1];
 `else
-    assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1];
+   assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1];
 `endif
 
 endmodule
diff --git a/lambdalib/stdlib/rtl/la_rsync.v b/lambdalib/stdlib/rtl/la_rsync.v
@@ -19,17 +19,17 @@ module la_rsync #(
     integer            sync_delay;
 
 `ifndef SYNTHESIS
-    always @(posedge clk) sync_delay <= {$random} % 2;
+   always @(posedge clk) sync_delay <= {$random} % 2;
 `endif
 
-    always @(posedge clk or negedge nrst_in)
-        if (!nrst_in) sync_pipe[STAGES:0] <= 'b0;
-        else sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
+   always @(posedge clk or negedge nrst_in)
+     if (!nrst_in) sync_pipe[STAGES:0] <= 'b0;
+     else sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
 
 `ifdef SYNTHESIS
-    assign nrst_out = sync_pipe[STAGES-1];
+   assign nrst_out = sync_pipe[STAGES-1];
 `else
-    assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1];
+   assign nrst_out = (|sync_delay & (|RND)) ? sync_pipe[STAGES] : sync_pipe[STAGES-1];
 `endif
 
 endmodule