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add back ie to input cell and fix typo
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gadfort committed Oct 28, 2024
1 parent 603ca6a commit 79a8998
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Showing 2 changed files with 6 additions and 4 deletions.
3 changes: 2 additions & 1 deletion lambdalib/iolib/rtl/la_ioinput.v
Original file line number Diff line number Diff line change
Expand Up @@ -23,14 +23,15 @@ module la_ioinput
inout vssio, // io ground
// core facing signals
output z, // output to core
input ie, // input enable, 1 = active
input pe, // pull enable, 1=enable
input ps, // pull select, 1=pullup, 0=pulldown
input [CFGW-1:0] cfg, // generic config interface
// io ring
inout [RINGW-1:0] ioring // generic ioring interface
);

assign z = pad;
assign z = ie ? pad : 1'b0;

`ifndef VERILATOR
if(PROP!="FIXED") begin
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7 changes: 4 additions & 3 deletions lambdalib/padring/rtl/la_ioside.v
Original file line number Diff line number Diff line change
Expand Up @@ -74,7 +74,7 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.z(zp[CELLMAP[(i*40)+:8]]),
.a(a[CELLMAP[(i*40)+:8]]),
.ie(ie[CELLMAP[(i*40)+:8]]),
Expand All @@ -99,8 +99,9 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.z(zp[CELLMAP[(i*40)+:8]]),
.ie(ie[CELLMAP[(i*40)+:8]]),
.pe(pe[CELLMAP[(i*40)+:8]]),
.ps(ps[CELLMAP[(i*40)+:8]]),
.cfg(cfg[CELLMAP[(i*40)+:8]*CFGW+:CFGW]),
Expand All @@ -120,7 +121,7 @@ module la_ioside
.RINGW(RINGW))
i0 (// pad
.pad(pad[CELLMAP[(i*40)+:8]]),
// core signalas
// core signals
.aio(aio[CELLMAP[(i*40)+:8]*3+:3]),
// supplies
.vss(vss),
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