make ramlib and fpgalib consistant with TYPE<->PROP

lambdalib/fpgalib/rtl/la_ble4p0.v

@@ -18,7 +18,7 @@
  ****************************************************************************/
 
 module la_ble4p0
-  #(parameter TYPE  = "DEFAULT" //  implementation selector
+  #(parameter PROP  = "DEFAULT" //  implementation selector
     )
    (// logic
     input        clk, // clock

lambdalib/fpgalib/rtl/la_lut4.v

@@ -41,7 +41,7 @@
  ****************************************************************************/
 
 module la_lut4
-  #(parameter TYPE  = "DEFAULT" //  implementation selector
+  #(parameter PROP  = "DEFAULT" //  implementation selector
     )
    (input [3:0]  in,
     input [15:0] lut,

lambdalib/ramlib/rtl/la_asyncfifo.v

@@ -7,15 +7,15 @@
  *
  * This is a wrapper for selecting from a set of hardened memory macros.
  *
- * A synthesizable reference model is used when the TYPE is DEFAULT. The
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
  * synthesizable model does not implement the cfg and test interface and should
  * only be used for basic testing and for synthesizing for FPGA devices.
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
  * one ore more hardcoded instantiations of RAM modules with a generate
- * statement relying on the "TYPE" to select between the list of modules
+ * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
@@ -27,7 +27,7 @@ module la_asyncfifo #(
     parameter CTRLW = 1,         // width of asic ctrl interface
     parameter TESTW = 1,         // width of asic teset interface
     parameter CHAOS = 0,         // generates random full logic when set
-    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+    parameter PROP  = "DEFAULT"  // Pass through variable for hard macro
 ) (  // write port
     input                  wr_clk,
     input                  wr_nreset,

lambdalib/ramlib/rtl/la_dpram.v

@@ -7,23 +7,23 @@
  *
  * This is a wrapper for selecting from a set of hardened memory macros.
  *
- * A synthesizable reference model is used when the TYPE is DEFAULT. The
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
  * synthesizable model does not implement the cfg and test interface and should
  * only be used for basic testing and for synthesizing for FPGA devices.
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_dpram" would generally include
  * one ore more hardcoded instantiations of RAM modules with a generate
- * statement relying on the "TYPE" to select between the list of modules
+ * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
 
 module la_dpram #(
     parameter DW    = 32,         // Memory width
     parameter AW    = 10,         // address width (derived)
-    parameter TYPE  = "DEFAULT",  // pass through variable for hard macro
+    parameter PROP  = "DEFAULT",  // pass through variable for hard macro
     parameter CTRLW = 128,        // width of asic ctrl interface
     parameter TESTW = 128         // width of asic test interface
 ) (  // Write port

lambdalib/ramlib/rtl/la_spram.v

@@ -7,23 +7,23 @@
  *
  * This is a wrapper for selecting from a set of hardened memory macros.
  *
- * A synthesizable reference model is used when the TYPE is DEFAULT. The
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
  * synthesizable model does not implement the cfg and test interface and should
  * only be used for basic testing and for synthesizing for FPGA devices.
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spram" would generally include
  * one ore more hardcoded instantiations of RAM modules with a generate
- * statement relying on the "TYPE" to select between the list of modules
+ * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
 
 module la_spram #(
     parameter DW    = 32,         // Memory width
     parameter AW    = 10,         // Address width (derived)
-    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter PROP  = "DEFAULT",  // Pass through variable for hard macro
     parameter CTRLW = 1,          // Width of asic ctrl interface
     parameter TESTW = 1           // Width of asic test interface
 ) (  // Memory interface

lambdalib/ramlib/rtl/la_spregfile.v

@@ -7,23 +7,23 @@
  *
  * This is a wrapper for selecting from a set of hardened register file macros.
  *
- * A synthesizable reference model is used when the TYPE is DEFAULT. The
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
  * synthesizable model does not implement the cfg and test interface and should
  * only be used for basic testing and for synthesizing for FPGA devices.
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_spregfile" would generally
  * include one ore more hardcoded instantiations of RF modules with a generate
- * statement relying on the "TYPE" to select between the list of modules
+ * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
 
 module la_spregfile #(
     parameter DW    = 32,         // Memory width
     parameter AW    = 10,         // Address width (derived)
-    parameter TYPE  = "DEFAULT",  // Pass through variable for hard macro
+    parameter PROP  = "DEFAULT",  // Pass through variable for hard macro
     parameter CTRLW = 128,        // Width of asic ctrl interface
     parameter TESTW = 128         // Width of asic test interface
 ) (  // Memory interface
@@ -46,7 +46,7 @@ module la_spregfile #(
     la_spram #(
         .DW(DW),
         .AW(AW),
-        .TYPE(TYPE),
+        .PROP(PROP),
         .CTRLW(CTRLW),
         .TESTW(TESTW)
     ) memory (

lambdalib/ramlib/rtl/la_syncfifo.v

@@ -17,7 +17,7 @@ module la_syncfifo
     parameter CHAOS = 1,         // generates random full logic when set
     parameter CTRLW = 1,         // width of asic ctrl interface
     parameter TESTW = 1,         // width of asic test interface
-    parameter TYPE  = "DEFAULT"  // Pass through variable for hard macro
+    parameter PROP  = "DEFAULT"  // Pass through variable for hard macro
     )
    (// basic interface
     input             clk,

lambdalib/syslib/rtl/la_qspi.v

@@ -5,7 +5,7 @@
  *
  * Docs:
  *
- * 1. Statically configurable as host/device by TYPE.
+ * 1. Statically configurable as host/device by PROP.
 
  ****************************************************************************/
 module la_qspi #(

lambdalib/utils/templates/la_spmemory.v

@@ -7,23 +7,23 @@
  *
  * This is a wrapper for selecting from a set of hardened memory macros.
  *
- * A synthesizable reference model is used when the TYPE is DEFAULT. The
+ * A synthesizable reference model is used when the PROP is DEFAULT. The
  * synthesizable model does not implement the cfg and test interface and should
  * only be used for basic testing and for synthesizing for FPGA devices.
  * Advanced ASIC development should rely on complete functional models
  * supplied on a per macro basis.
  *
  * Technologoy specific implementations of "la_sp{{ type }}" would generally include
  * one ore more hardcoded instantiations of {{ type }} modules with a generate
- * statement relying on the "TYPE" to select between the list of modules
+ * statement relying on the "PROP" to select between the list of modules
  * at build time.
  *
  ****************************************************************************/
 
 module la_sp{{ type }}
   #(parameter DW     = 32,          // Memory width
     parameter AW     = 10,          // Address width (derived)
-    parameter TYPE   = "DEFAULT",   // Pass through variable for hard macro
+    parameter PROP   = "DEFAULT",   // Pass through variable for hard macro
     parameter CTRLW  = 128,         // Width of asic ctrl interface
     parameter TESTW  = 128          // Width of asic test interface
     )
@@ -45,15 +45,15 @@ module la_sp{{ type }}
     );
 
     // Determine which memory to select
-    localparam MEM_TYPE = (TYPE != "DEFAULT") ? TYPE :{% for aw, dw_select in selection_table.items() %}
+    localparam MEM_PROP = (PROP != "DEFAULT") ? PROP :{% for aw, dw_select in selection_table.items() %}
       {% if loop.nextitem is defined %}(AW {% if loop.previtem is defined %}=={% else %}>={% endif %} {{ aw }}) ? {% endif %}{% for dw, memory in dw_select.items() %}{% if loop.nextitem is defined %}(DW >= {{dw}}) ? {% endif %}"{{ memory}}"{% if loop.nextitem is defined %} : {% endif%}{% endfor %}{% if loop.nextitem is defined %} :{% else %};{% endif %}{% endfor %}
 
     localparam MEM_WIDTH = {% for memory, width in width_table %}
-      (MEM_TYPE == "{{ memory }}") ? {{ width }} :{% endfor %}
+      (MEM_PROP == "{{ memory }}") ? {{ width }} :{% endfor %}
       0;
 
     localparam MEM_DEPTH = {% for memory, depth in depth_table %}
-      (MEM_TYPE == "{{ memory }}") ? {{ depth }} :{% endfor %}
+      (MEM_PROP == "{{ memory }}") ? {{ depth }} :{% endfor %}
       0;
 
     // Create memories
@@ -106,10 +106,11 @@ module la_sp{{ type }}
           assign ce_in = ce && selected;
           assign we_in = we && selected;
           {% for memory, inst_name in inst_map.items() %}
-          {% if loop.previtem is defined %}else {% endif %}if (MEM_TYPE == "{{ memory }}")
+          if (MEM_PROP == "{{ memory }}") begin: i{{ memory }}
             {{ inst_name }} memory ({% for port, net in port_mapping[memory] %}
               .{{ port }}({{ net }}){% if loop.nextitem is defined %},{% endif %}{% endfor %}
-            );{% endfor %}
+            );
+          end{% endfor %}
         end
       end
     endgenerate