Shorting SIMULATIO to SIM

- Clear enough, shorter is better
siliconcompiler · May 6, 2024 · fe8b495 · fe8b495
1 parent 5b55705
commit fe8b495
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Showing 3 changed files with 8 additions and 12 deletions.
diff --git a/lambdalib/stdlib/rtl/la_dsync.v b/lambdalib/stdlib/rtl/la_dsync.v
@@ -5,7 +5,7 @@
 //#############################################################################
 
 module la_dsync #(parameter PROP = "DEFAULT",
-                  parameter STAGES = 2,       // synchhronizer depth
+                  parameter STAGES = 2,       // synchronizer depth
                   parameter RND = 1)          // randomize simulation delay
    (
     input  clk, // clock
@@ -14,20 +14,16 @@ module la_dsync #(parameter PROP = "DEFAULT",
     );
 
    reg [STAGES:0] shiftreg;
-   integer        sync_delay;
-
-   always @(posedge clk) begin
+   always @(posedge clk)
       shiftreg[STAGES:0] <= {shiftreg[STAGES-1:0], in};
-`ifdef SIMULATION
-      sync_delay <= {$random} % 2;
-`endif
-   end
 
-`ifdef SIMULATION
+`ifdef SIM
+   integer        sync_delay;
+   sync_delay <= {$random} % 2;
    assign out = (|sync_delay & (|RND)) ? shiftreg[STAGES] : shiftreg[STAGES-1];
-
 `else
    assign out = shiftreg[STAGES-1];
 `endif
 
+
 endmodule
diff --git a/lambdalib/stdlib/rtl/la_pwrbuf.v b/lambdalib/stdlib/rtl/la_pwrbuf.v
@@ -14,7 +14,7 @@ module la_pwrbuf #(
     output z
     );
 
-`ifdef SIMULATION
+`ifdef SIM
    assign z = ((vdd === 1'b1) && (vss === 1'b0)) ? a : 1'bX;
 `else
    assign z = a;

diff --git a/lambdalib/stdlib/rtl/la_rsync.v b/lambdalib/stdlib/rtl/la_rsync.v
@@ -24,7 +24,7 @@ module la_rsync #(parameter PROP = "DEFAULT",
      else
        sync_pipe[STAGES:0] <= {sync_pipe[STAGES-1:0], 1'b1};
 
-`ifdef SIMULATION
+`ifdef SIM
    always @(posedge clk)
      sync_delay <= {$random} % 2;