Improving iolib cells

[aolofsson]

Making input buffer "bullet proof"

• For some signals like reset and certain static strap signals, we really can't afford to make a mistake. Since io cell modeling and simulation of tristate io buffer isn't always perfect, we want to make sure that the design is correct by construction as much as possible for these buffers. The bidir signal is very configurable and the cfg bus is generic per library (increasing the chance of a catastrophic mistake).
• This input buffer hard codes all choices in teh abstracted library, minimizing the chance that the user/designer makes a mistake. The designer of the lambdapdk still needs to get the signal mapping correct, but this only has to be done once per port, not for every design.
• Confident designers can always use the bidir cells and tie off signals to the grnd/power as appropriate for input cells that need more flexibility.

Making bidir cell more robust

• Making the pull select and pull enable signal hard coded signals instead of the generic cfg bus. Much more intutituve for the user and a less leakly abstractiton.
• Adding a simple minimalist testbench
• Adding modeling of weak pull up and pulldowns