Requirements

System requirements:

• FastServo shall resemble the Stabilizer architecture and mechanical design
• FastServo shall support PoE, Ethernet, USB interfaces (the same as Stabilizer)
• FastServo shall support Trenz FPGA modules - e.g. TE0710-02-35-2CF or TE0712-02-100-2C
• FastServo shall support 2x fast ADC channels
• FastServo shall support 2x fast DAC channels
• FastServo shall support 1 or 2 EEM connectors routed to the FPGA (to be discussed)
• FastServo shall support Stabilizer mezzanines e.g. Pounder

DAC subsystem requirements:

• DAC channel shall have latency + BW suitable for 3MHz closed-loop applications (including latency of loop filter on FPGA)
• DAC channel shall have fixed +-1V input/output range
• DAC channel bandwidth shall be 100 MHz or 125MHz 14bit
• DAC channel shall use AD9117 DAC

ADC channel requirements

• ADC channel AFE shall have minimum latency, high bandwidth and selecable volatage input ranges, input protection and input filter
• ADC channel shall use LTC2195 as an ADC
• ADC channel bandwidth shall be 100 or 125MHz 16bit
• ADC channel input volatage range should be selecable: +/- 0.1 V or +/- 0.25 V, +/- 1 V, +/- 10 V