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Requirements
zdun8 edited this page Jan 5, 2020
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System requirements:
- FastServo shall resemble the Stabilizer architecture and mechanical design
- FastServo shall support PoE, Ethernet, USB interfaces (the same as Stabilizer)
- FastServo shall support Trenz FPGA modules - e.g. TE0710-02-35-2CF or TE0712-02-100-2C
- FastServo shall support 2x fast ADC channels
- FastServo shall support 2x fast DAC channels
- FastServo shall support 1 or 2 EEM connectors routed to the FPGA (to be discussed)
DAC subsystem requirements:
- DAC channel shall have latency + BW suitable for 3MHz closed-loop applications (including latency of loop filter on FPGA)
- DAC channel shall have fixed +-1V input/output range
- DAC channel bandwidth shall be 100 MHz or 125MHz 16bit
ADC channel requirements
- ADC channel AFE shall be based on FmcAdc100M14 design
- ADC channel shall use LTC2107 as an ADC
- ADC channel bandwidth shall be 100 or 125MHz 16bit