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acpidump
Dave Cottlehuber edited this page Oct 27, 2021
·
1 revision
/*
RSD PTR: OEM=ORACLE, ACPI_Rev=2.0x (2)
XSDT=0x0000083fadb70000, length=36, cksum=49
*/
/*
XSDT: Length=236, Revision=1, Checksum=229,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x1000013
Entries={ 0x0000083fadb50000, 0x0000083fadb60000, 0x0000083fadb40000, 0x0000083fadb30000, 0x0000083fadb10000, 0x0000083fadb00000, 0x0000083fadaf0000, 0x0000083fadab0000, 0x0000083fadaa0000, 0x0000083fada90000, 0x0000083fada80000, 0x0000083fada70000, 0x0000083fada60000, 0x0000083fada50000, 0x0000083fada30000, 0x0000083fada20000, 0x0000083fada10000, 0x0000083fadb20000, 0x0000083fada00000, 0x0000083fad9f0000, 0x0000083fada40000, 0x0000083fad9e0000, 0x0000083fad9d0000, 0x0000083fad9c0000, 0x0000083fad9b0000 }
*/
/*
FACP: Length=276, Revision=6, Checksum=207,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20190509
FACS=0xbffd0000, DSDT=0x0
INT_MODEL=PIC
Preferred_PM_Profile=Reserved (7)
SCI_INT=0
SMI_CMD=0x0, ACPI_ENABLE=0x0, ACPI_DISABLE=0x0, S4BIOS_REQ=0x0
PSTATE_CNT=0x0
PM1a_EVT_BLK=0x0-0xffffffff
PM1a_CNT_BLK=0x0-0xffffffff
PM_TMR_BLK=0x0-0xffffffff
P_LVL2_LAT=0 us, P_LVL3_LAT=0 us
FLUSH_SIZE=0, FLUSH_STRIDE=0
DUTY_OFFSET=0, DUTY_WIDTH=0
DAY_ALRM=0, MON_ALRM=0, CENTURY=0
IAPC_BOOT_ARCH=
Flags={POWER_BUTTON,HW_REDUCED}
X_FACS=0x0000000000000000, X_DSDT=0x0000083fadac0000
X_PM1a_EVT_BLK=0x0000000000000000:0[0] (Memory)
X_PM1a_CNT_BLK=0x0000000000000000:0[0] (Memory)
X_PM_TMR_BLK=0x0000000000000000:0[0] (Memory)
*/
/*
DSDT: Length=187603, Revision=2, Checksum=82,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20200717
*/
/*
DBG2: Length=92, Revision=0, Checksum=228,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20190509
*/
/*
GTDT: Length=272, Revision=3, Checksum=109,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20190509
*/
/*
SSDT: Length=45, Revision=2, Checksum=107,
OEMID=Oracle, OEM Table ID=A1_2c, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20190509
*/
/*
EINJ: Length=336, Revision=1, Checksum=134,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20200717
HeaderLength=48
Flags=0x00
Entries=9
Action=0
Instruction=0
Flags=00
RegisterRegion=0x0000000088220000:0[64] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
Action=1
Instruction=0
Flags=00
RegisterRegion=0x0000000088220040:0[64] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
Action=8
Instruction=2
Flags=01
RegisterRegion=0x0000000088221000:0[32] (Memory)
Value=0x0000000000000000
Mask=0x00000000ffffffff
Action=2
Instruction=2
Flags=01
RegisterRegion=0x0000000088220080:0[32] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
Action=3
Instruction=0
Flags=00
RegisterRegion=0x00000000882200c0:0[64] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
Action=4
Instruction=3
Flags=01
RegisterRegion=0x0000000088220100:0[64] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
Action=5
Instruction=3
Flags=01
RegisterRegion=0x0000100000543010:0[32] (Memory)
Value=0x00000000b1a00000
Mask=0x00000000ffffffff
Action=6
Instruction=1
Flags=00
RegisterRegion=0x0000000088220140:0[64] (Memory)
Value=0x0000000000000001
Mask=0xffffffffffffffff
Action=7
Instruction=0
Flags=01
RegisterRegion=0x0000000088220180:0[64] (Memory)
Value=0x0000000000000000
Mask=0xffffffffffffffff
*/
/*
HEST: Length=776, Revision=1, Checksum=23,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20200717
ErrorSourceCount=8
Type=10
SourceId=0
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200000:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000100000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2983198720
Type=10
SourceId=1
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200008:0[64] (Memory)
Notify:
Type=0
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000100000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2982150144
Type=10
SourceId=2
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200010:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000100000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2985295872
Type=10
SourceId=6
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200030:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000100000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2979004416
Type=10
SourceId=7
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200038:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000100000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2979004417
Type=10
SourceId=3
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200018:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000500000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2983198720
Type=10
SourceId=4
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200020:0[64] (Memory)
Notify:
Type=0
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000500000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2982150144
Type=10
SourceId=5
RelatedSourceId=65535
Enabled=1
RecordsToPreallocate=1
MaxSectionsPerRecord=1
MaxRawDataLength=4096
ErrorStatusAddress=0x0000000088200028:0[64] (Memory)
Notify:
Type=3
Length=28
ConfigWriteEnable=0000
PollInterval=3000
Vector=0
PollingThresholdValue=0
PollingThresholdWindow=0
ErrorThresholdValue=0
ErrorThresholdWindow=0
ErrorBlockLength=4096
ReadAckRegister=0x0000500000543010:0[64] (Memory)
ReadAckPreserve=0
ReadAckWrite=2985295872
*/
/*
SDEI: Length=36, Revision=1, Checksum=124,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20200717
*/
/*
MCFG: Length=268, Revision=1, Checksum=45,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20190509
Base Address=0x00003bfff0000000
Segment Group=0x0001
Start Bus=0
End Bus=255
Base Address=0x00003ffff0000000
Segment Group=0x0000
Start Bus=0
End Bus=255
Base Address=0x000023fff0000000
Segment Group=0x0002
Start Bus=0
End Bus=255
Base Address=0x000027fff0000000
Segment Group=0x0003
Start Bus=0
End Bus=255
Base Address=0x00002bfff0000000
Segment Group=0x0004
Start Bus=0
End Bus=255
Base Address=0x00002ffff0000000
Segment Group=0x0005
Start Bus=0
End Bus=255
Base Address=0x00007bfff0000000
Segment Group=0x0006
Start Bus=0
End Bus=255
Base Address=0x00007ffff0000000
Segment Group=0x0007
Start Bus=0
End Bus=255
Base Address=0x000063fff0000000
Segment Group=0x0008
Start Bus=0
End Bus=255
Base Address=0x000067fff0000000
Segment Group=0x0009
Start Bus=0
End Bus=255
Base Address=0x00006bfff0000000
Segment Group=0x000a
Start Bus=0
End Bus=255
Base Address=0x00006ffff0000000
Segment Group=0x000b
Start Bus=0
End Bus=255
Base Address=0x000033fff0000000
Segment Group=0x000c
Start Bus=0
End Bus=255
Base Address=0x000037fff0000000
Segment Group=0x000d
Start Bus=0
End Bus=255
*/
/*
SPMI: Length=65, Revision=5, Checksum=27,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI., Creator Revision=0x0
*/
/*
SPMI: Length=65, Revision=5, Checksum=227,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI., Creator Revision=0x0
*/
/*
SPMI: Length=65, Revision=5, Checksum=187,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI., Creator Revision=0x0
*/
/*
FIDT: Length=156, Revision=1, Checksum=154,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x10013
*/
/*
SPCR: Length=80, Revision=2, Checksum=79,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI., Creator Revision=0x5000f
*/
/*
TPM2: Length=100, Revision=4, Checksum=130,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x0
ControlArea=88500000
StartMethod=b
*/
/*
PPTT: Length=28256, Revision=2, Checksum=13,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
*/
/*
SLIT: Length=48, Revision=1, Checksum=144,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
Locality Count=2
0 1
+--------
0 | 10 20
1 | 20 10
*/
/*
SRAT: Length=3312, Revision=3, Checksum=160,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
Table Revision=1
Type=Memory
Flags={ENABLED}
Base Address=0x0000000088300000
Length=0x0000000000100000
Proximity Domain=0
Type=Memory
Flags={ENABLED}
Base Address=0x0000000090000000
Length=0x0000000030000000
Proximity Domain=0
Type=Memory
Flags={ENABLED}
Base Address=0x0000080000000000
Length=0x0000000080000000
Proximity Domain=0
Type=Memory
Flags={ENABLED}
Base Address=0x00000800c0000000
Length=0x0000007f40000000
Proximity Domain=0
Type=Memory
Flags={ENABLED}
Base Address=0x0000400000000000
Length=0x00000000c0000000
Proximity Domain=1
Type=Memory
Flags={ENABLED}
Base Address=0x0000400100000000
Length=0x0000007f00000000
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=0
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=256
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=257
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=512
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=513
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=768
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=769
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1024
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1025
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1280
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1281
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1536
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1537
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1792
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=1793
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2048
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2049
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2304
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2305
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2560
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2561
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2816
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=2817
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3072
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3073
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3328
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3329
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3584
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3585
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3840
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=3841
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4096
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4097
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4352
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4353
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4608
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4609
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4864
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=4865
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5120
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5121
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5376
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5377
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5632
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5633
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5888
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=5889
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6144
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6145
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6400
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6401
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6656
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6657
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6912
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=6913
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7168
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7169
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7424
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7425
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7680
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7681
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7936
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=7937
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8192
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8193
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8448
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8449
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8704
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8705
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8960
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=8961
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9216
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9217
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9472
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9473
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9728
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9729
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9984
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=9985
Proximity Domain=0
Type=GICC
Flags={ENABLED}
APIC ID=65536
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=65537
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=65792
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=65793
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66048
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66049
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66304
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66305
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66560
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66561
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66816
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=66817
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67072
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67073
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67328
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67329
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67584
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67585
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67840
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=67841
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68096
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68097
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68352
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68353
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68608
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68609
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68864
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=68865
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69120
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69121
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69376
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69377
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69632
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69633
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69888
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=69889
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70144
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70145
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70400
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70401
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70656
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70657
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70912
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=70913
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71168
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71169
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71424
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71425
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71680
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71681
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71936
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=71937
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72192
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72193
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72448
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72449
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72704
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72705
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72960
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=72961
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73216
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73217
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73472
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73473
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73728
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73729
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73984
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=73985
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74240
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74241
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74496
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74497
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74752
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=74753
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75008
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75009
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75264
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75265
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75520
Proximity Domain=1
Type=GICC
Flags={ENABLED}
APIC ID=75521
Proximity Domain=1
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
Type=GIC ITS
*/
/*
BERT: Length=48, Revision=1, Checksum=48,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=INTL, Creator Revision=0x20200717
RegionLength=141
Address=0x0000000088230000
*/
/*
MCFG: Length=220, Revision=1, Checksum=143,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
Base Address=0x00003bfff0000000
Segment Group=0x0001
Start Bus=0
End Bus=255
Base Address=0x00003ffff0000000
Segment Group=0x0000
Start Bus=0
End Bus=255
Base Address=0x000023fff0000000
Segment Group=0x0002
Start Bus=0
End Bus=255
Base Address=0x000027fff0000000
Segment Group=0x0003
Start Bus=0
End Bus=255
Base Address=0x00002bfff0000000
Segment Group=0x0004
Start Bus=0
End Bus=255
Base Address=0x00002ffff0000000
Segment Group=0x0005
Start Bus=0
End Bus=255
Base Address=0x00007bfff0000000
Segment Group=0x0006
Start Bus=0
End Bus=255
Base Address=0x000063fff0000000
Segment Group=0x0008
Start Bus=0
End Bus=255
Base Address=0x000067fff0000000
Segment Group=0x0009
Start Bus=0
End Bus=255
Base Address=0x00006bfff0000000
Segment Group=0x000a
Start Bus=0
End Bus=255
Base Address=0x00006ffff0000000
Segment Group=0x000b
Start Bus=0
End Bus=255
*/
/*
IORT: Length=2116, Revision=0, Checksum=41,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
*/
/*
APIC: Length=13140, Revision=5, Checksum=117,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x1000013
Local APIC ADDR=0x00000000
Flags={}
Type=GIC CPU Interface Structure
UID=4608
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=120000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6656
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1a0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5120
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=140000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7168
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1c0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4096
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6144
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=180000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5632
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=160000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7680
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1e0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2560
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=a0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8704
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=220000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3072
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=c0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9216
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=240000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2048
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=80000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8192
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=200000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3584
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=e0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9728
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=260000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=512
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=20000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1024
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=40000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=0
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=0
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1536
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=60000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4864
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=130000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6912
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1b0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5376
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=150000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7424
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1d0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4352
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=110000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6400
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=190000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5888
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=170000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7936
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1f0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2816
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=b0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8960
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=230000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3328
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICH=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=d0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9472
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Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
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GICH=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=250000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2304
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=90000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8448
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=210000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3840
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Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=f0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9984
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICH=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=270000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=768
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
GICH=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=30000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1280
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=50000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=256
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=10000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1792
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICR ADDR=0000000000000000
MPIDR=70000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4609
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Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=120100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6657
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1a0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5121
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=140100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7169
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1c0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4097
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6145
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=180100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5633
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=160100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7681
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1e0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2561
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=a0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8705
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=220100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3073
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=c0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9217
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=240100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2049
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=80100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8193
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=200100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3585
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=e0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9729
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=260100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=513
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=20100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1025
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=40100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1537
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=60100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4865
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=130100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6913
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1b0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5377
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=150100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7425
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1d0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=4353
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=110100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=6401
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=190100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=5889
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=170100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=7937
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1f0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2817
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=b0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8961
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=230100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3329
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=d0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9473
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=250100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=2305
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=90100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=8449
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=210100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=3841
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=f0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=9985
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=270100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=769
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=30100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1281
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=50100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=257
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=10100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=1793
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=70100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70144
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100120000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72192
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001a0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70656
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100140000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72704
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001c0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69632
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100100000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71680
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100180000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71168
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100160000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73216
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001e0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68096
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000a0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74240
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100220000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68608
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000c0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74752
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100240000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67584
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100080000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73728
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100200000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69120
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000e0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75264
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100260000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66048
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100020000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66560
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100040000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=65536
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100000000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67072
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100060000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70400
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100130000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72448
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001b0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70912
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100150000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72960
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001d0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69888
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100110000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71936
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100190000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71424
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100170000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73472
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001f0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68352
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000b0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74496
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100230000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68864
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000d0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75008
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100250000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67840
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100090000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73984
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100210000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69376
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000f0000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75520
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100270000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66304
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100030000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66816
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100050000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=65792
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100010000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67328
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100070000
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70145
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100120100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72193
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001a0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70657
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
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GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100140100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72705
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001c0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69633
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100100100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71681
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100180100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71169
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100160100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73217
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001e0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68097
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000a0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74241
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100220100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68609
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000c0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74753
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100240100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67585
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100080100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73729
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100200100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69121
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000e0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75265
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100260100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66049
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100020100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66561
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100040100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=65537
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100000100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67073
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100060100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70401
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100130100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72449
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001b0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=70913
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100150100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=72961
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001d0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69889
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100110100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71937
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100190100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=71425
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100170100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73473
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1001f0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68353
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000b0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=74497
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100230100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=68865
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000d0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75009
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100250100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67841
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100090100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=73985
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100210100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=69377
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=1000f0100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=75521
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100270100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66305
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100030100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=66817
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100050100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=65793
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100010100
Efficency Class=0
Type=GIC CPU Interface Structure
UID=67329
CPU INTERFACE=0
Flags={Performance intr=level, VGIC intr=level}
Parking Protocol Version=0
PERF INTR=23
Parked ADDR=0000000000000000
Base ADDR=0000000000000000
GICV=0000000000000000
GICH=0000000000000000
VGIC INTR=25
GICR ADDR=0000000000000000
MPIDR=100070100
Efficency Class=0
Type=GIC Distributor Structure
GIC ID=0
Base ADDR=0000100100000000
Vector Base=0
GIC VERSION=3
Type=GIC Redistributor Structure
Base ADDR=0000100100140000
Length=01000000
Type=GIC Redistributor Structure
Base ADDR=0000500100140000
Length=01000000
Type=GIC ITS Structure
GIC ITS ID=2
Base ADDR=0000100100080000
Type=GIC ITS Structure
GIC ITS ID=3
Base ADDR=00001001000a0000
Type=GIC ITS Structure
GIC ITS ID=4
Base ADDR=00001001000c0000
Type=GIC ITS Structure
GIC ITS ID=5
Base ADDR=00001001000e0000
Type=GIC ITS Structure
GIC ITS ID=6
Base ADDR=0000100100100000
Type=GIC ITS Structure
GIC ITS ID=7
Base ADDR=0000100100120000
Type=GIC ITS Structure
GIC ITS ID=10
Base ADDR=0000500100080000
Type=GIC ITS Structure
GIC ITS ID=11
Base ADDR=00005001000a0000
Type=GIC ITS Structure
GIC ITS ID=12
Base ADDR=00005001000c0000
Type=GIC ITS Structure
GIC ITS ID=13
Base ADDR=00005001000e0000
Type=GIC ITS Structure
GIC ITS ID=14
Base ADDR=0000500100100000
Type=GIC ITS Structure
GIC ITS ID=15
Base ADDR=0000500100120000
*/
/*
PCCT: Length=2748, Revision=2, Checksum=245,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMP., Creator Revision=0x1000013
*/
/*
WSMT: Length=40, Revision=1, Checksum=213,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x10013
*/
/*
FPDT: Length=68, Revision=1, Checksum=13,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=AMI, Creator Revision=0x1000013
*/
/*
iBFT: Length=565, Revision=1, Checksum=83,
OEMID=ORACLE, OEM Table ID=A1_2C, OEM Revision=0x77013100,
Creator ID=, Creator Revision=0x0
*/
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20210930 (64-bit version)
* Copyright (c) 2000 - 2021 Intel Corporation
*
* Disassembling to symbolic ASL+ operators
*
* Disassembly of /tmp/acpidump.FRwXM7/acpdump.din, Wed Oct 27 17:46:02 2021
*
* Original Table Header:
* Signature "DSDT"
* Length 0x0002DCDC (187612)
* Revision 0x02
* Checksum 0x64
* OEM ID "ORACLE"
* OEM Table ID "A1_2C"
* OEM Revision 0x77013100 (1996566784)
* Compiler ID "INTL"
* Compiler Version 0x20200717 (538969879)
*/
DefinitionBlock ("", "DSDT", 2, "ORACLE", "A1_2C", 0x77013100)
{
Name (BDMD, "A1_2c Mother Board")
Name (TPMF, One)
Scope (_SB)
{
Device (HM00)
{
Name (_HID, "APMC0D29") // _HID: Hardware ID
Name (_UID, "HWM0") // _UID: Unique ID
Name (_DDN, "HWM0") // _DDN: DOS Device Name
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Hardware Monitor Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"pcc-channel",
0x0E
}
}
})
}
Device (HM01)
{
Name (_HID, "APMC0D29") // _HID: Hardware ID
Name (_UID, "HWM1") // _UID: Unique ID
Name (_DDN, "HWM1") // _DDN: DOS Device Name
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Hardware Monitor Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"pcc-channel",
0x1D
}
}
})
}
Device (HM02)
{
Name (_HID, "AMPC0005") // _HID: Hardware ID
Name (_UID, "HWM2") // _UID: Unique ID
Name (_DDN, "HWM2") // _DDN: DOS Device Name
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Altra SoC Hardware Monitor Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000088900000, // Range Minimum
0x000000008891FFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000020000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
Device (HM03)
{
Name (_HID, "AMPC0005") // _HID: Hardware ID
Name (_UID, "HWM3") // _UID: Unique ID
Name (_DDN, "HWM3") // _DDN: DOS Device Name
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Altra SoC Hardware Monitor Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00000000C0000000, // Range Minimum
0x00000000C001FFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000020000, // Length
,, , AddressRangeMemory, TypeStatic)
})
}
Device (I2C4)
{
Name (_HID, "XPMC0D0F") // _HID: Hardware ID
Name (_UID, 0x04) // _UID: Unique ID
Name (_STR, Unicode ("Altra I2C4 Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00001000026B0000, // Range Minimum
0x00001000026BFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000010000, // Length
,, , AddressRangeMemory, TypeStatic)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000069,
}
})
Device (IPI)
{
Name (_HID, "AMPC0004") // _HID: Hardware ID
Name (_CID, "IPI0001") // _CID: Compatible ID
Name (_STR, Unicode ("IPMI_SSIF")) // _STR: Description String
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Method (_IFT, 0, NotSerialized) // _IFT: IPMI Interface Type
{
Return (0x04)
}
Method (_ADR, 0, NotSerialized) // _ADR: Address
{
Return (0x10)
}
Method (_SRV, 0, NotSerialized) // _SRV: IPMI Spec Revision
{
Return (0x0200)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBusV2 (0x0010, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.I2C4",
0x00, ResourceConsumer, , Exclusive,
RawDataBuffer (0x06) // Vendor Data
{
0x42, 0x4D, 0x43, 0x30, 0x01, 0x00
})
})
}
Name (SSCN, Package (0x03)
{
0x01AB,
0x01F3,
Zero
})
Name (FMCN, Package (0x03)
{
0xA4,
0x013F,
Zero
})
}
Device (I2C6)
{
Name (_HID, "APMC0D0F") // _HID: Hardware ID
Name (_UID, 0x06) // _UID: Unique ID
Name (_STR, Unicode ("Altra I2C6 Device")) // _STR: Description String
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000100002750000, // Range Minimum
0x000010000275FFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000010000, // Length
,, , AddressRangeMemory, TypeStatic)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000006B,
}
})
Name (AVBL, Zero)
Method (_REG, 2, NotSerialized) // _REG: Region Availability
{
If ((Arg0 == 0x09))
{
AVBL = Arg1
}
}
}
Device (GED0)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000054,
}
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x0000002C,
}
})
OperationRegion (MHPP, SystemMemory, 0x88970000, 0x03C0)
Field (MHPP, DWordAcc, NoLock, Preserve)
{
A020, 32,
A00I, 8,
Offset (0x18),
A030, 32,
A01I, 8,
Offset (0x30),
B000, 32,
B02I, 8,
Offset (0x48),
B002, 32,
B03I, 8,
Offset (0x60),
B004, 32,
B04I, 8,
Offset (0x78),
B006, 32,
B05I, 8,
Offset (0x90),
B010, 32,
B06I, 8,
Offset (0xA8),
B012, 32,
B07I, 8,
Offset (0xC0),
B014, 32,
B08I, 8,
Offset (0xD8),
B016, 32,
B09I, 8,
Offset (0xF0),
B020, 32,
B10I, 8,
Offset (0x108),
B022, 32,
B11I, 8,
Offset (0x120),
B024, 32,
B12I, 8,
Offset (0x138),
B030, 32,
B13I, 8,
Offset (0x150),
B034, 32,
B14I, 8,
Offset (0x168),
B036, 32,
B15I, 8,
Offset (0x180),
A120, 32,
A16I, 8,
Offset (0x198),
A121, 32,
A17I, 8,
Offset (0x1B0),
A122, 32,
A18I, 8,
Offset (0x1C8),
A123, 32,
A19I, 8,
Offset (0x1E0),
A130, 32,
A20I, 8,
Offset (0x1F8),
A132, 32,
A21I, 8,
Offset (0x210),
B100, 32,
B22I, 8,
Offset (0x228),
B104, 32,
B23I, 8,
Offset (0x240),
B106, 32,
B24I, 8,
Offset (0x258),
B110, 32,
B25I, 8,
Offset (0x270),
B112, 32,
B26I, 8,
Offset (0x288),
B114, 32,
B27I, 8,
Offset (0x2A0),
B120, 32,
B28I, 8,
Offset (0x2B8),
B122, 32,
B29I, 8,
Offset (0x2D0),
B124, 32,
B30I, 8,
Offset (0x2E8),
B126, 32,
B31I, 8,
Offset (0x300),
B130, 32,
B32I, 8,
Offset (0x318),
B132, 32,
B33I, 8,
Offset (0x330),
B134, 32,
B34I, 8,
Offset (0x348),
B136, 32,
B35I, 8
}
OperationRegion (DBN4, SystemMemory, 0x0000100000544010, 0x14)
Field (DBN4, DWordAcc, NoLock, Preserve)
{
DOUT, 32,
Offset (0x10),
STA4, 32
}
}
Device (GED1)
{
Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
Name (_CID, "ACPI0013" /* Generic Event Device */) // _CID: Compatible ID
Name (_UID, One) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000147,
}
})
OperationRegion (PDDR, SystemMemory, 0x00001000027B0004, 0x04)
Field (PDDR, DWordAcc, NoLock, Preserve)
{
STDI, 8
}
OperationRegion (INTE, SystemMemory, 0x00001000027B0030, 0x04)
Field (INTE, DWordAcc, NoLock, Preserve)
{
STDE, 8
}
OperationRegion (INTT, SystemMemory, 0x00001000027B0034, 0x04)
Field (INTT, DWordAcc, NoLock, Preserve)
{
TYPE, 8
}
OperationRegion (INTP, SystemMemory, 0x00001000027B0038, 0x04)
Field (INTP, DWordAcc, NoLock, Preserve)
{
POLA, 8
}
OperationRegion (INTS, SystemMemory, 0x00001000027B003C, 0x04)
Field (INTS, DWordAcc, NoLock, Preserve)
{
STDS, 8
}
OperationRegion (INTC, SystemMemory, 0x00001000027B0040, 0x04)
Field (INTC, DWordAcc, NoLock, Preserve)
{
SINT, 8
}
OperationRegion (INTM, SystemMemory, 0x00001000027B0044, 0x04)
Field (INTM, DWordAcc, NoLock, Preserve)
{
MASK, 8
}
Method (_INI, 0, NotSerialized) // _INI: Initialize
{
TYPE = Zero
POLA = Zero
STDI = Zero
STDE = 0x80
MASK = Zero
}
Method (_EVT, 1, Serialized) // _EVT: Event
{
Switch (ToInteger (Arg0))
{
Case (0x0147)
{
If ((STDS & 0x80))
{
SINT = 0x80
STDE = Zero
Notify (PWRB, 0x80) // Status Change
}
}
}
}
}
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0B)
}
}
Device (URT0)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000100002600000, // Range Minimum
0x0000100002600FFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000001000, // Length
,, , AddressRangeMemory, TypeStatic)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000062,
}
})
}
Device (URT2)
{
Name (_HID, "ARMH0011") // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000100002620000, // Range Minimum
0x0000100002620FFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000000001000, // Length
,, , AddressRangeMemory, TypeStatic)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
{
0x00000064,
}
})
}
Device (HED0)
{
Name (_HID, EisaId ("PNP0C33") /* Error Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
}
Device (NVDR)
{
Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
Return (Buffer (One)
{
0x00 // .
})
}
Device (NVD1)
{
Name (_ADR, 0x0330) // _ADR: Address
Name (SMRT, Buffer (0x0D)
{
0x00 // .
})
CreateDWordField (SMRT, Zero, BSTA)
CreateWordField (SMRT, 0x04, BHTH)
CreateWordField (SMRT, 0x06, BTMP)
CreateByteField (SMRT, 0x08, BETH)
CreateByteField (SMRT, 0x09, BWTH)
CreateByteField (SMRT, 0x0A, BNLF)
OperationRegion (BUF1, SystemMemory, 0x88980000, 0x10)
Field (BUF1, DWordAcc, NoLock, Preserve)
{
STAT, 32,
HLTH, 16,
CTMP, 16,
ETHS, 8,
WTHS, 8,
NVLF, 8,
Offset (0x10)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05") /* Microsoft NVDIMM Command set */))
{
If ((Arg2 == Zero))
{
Return (Buffer (0x02)
{
0x01, 0x08 // ..
})
}
If ((Arg2 == 0x0B))
{
BSTA = STAT /* \_SB_.NVDR.NVD1.STAT */
BHTH = HLTH /* \_SB_.NVDR.NVD1.HLTH */
BTMP = CTMP /* \_SB_.NVDR.NVD1.CTMP */
BETH = ETHS /* \_SB_.NVDR.NVD1.ETHS */
BWTH = WTHS /* \_SB_.NVDR.NVD1.WTHS */
BNLF = NVLF /* \_SB_.NVDR.NVD1.NVLF */
Return (SMRT) /* \_SB_.NVDR.NVD1.SMRT */
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
}
Device (NVD2)
{
Name (_ADR, 0x0770) // _ADR: Address
Name (SMRT, Buffer (0x0D)
{
0x00 // .
})
CreateDWordField (SMRT, Zero, BSTA)
CreateWordField (SMRT, 0x04, BHTH)
CreateWordField (SMRT, 0x06, BTMP)
CreateByteField (SMRT, 0x08, BETH)
CreateByteField (SMRT, 0x09, BWTH)
CreateByteField (SMRT, 0x0A, BNLF)
OperationRegion (BUF1, SystemMemory, 0x88988000, 0x10)
Field (BUF1, DWordAcc, NoLock, Preserve)
{
STAT, 32,
HLTH, 16,
CTMP, 16,
ETHS, 8,
WTHS, 8,
NVLF, 8,
Offset (0x10)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05") /* Microsoft NVDIMM Command set */))
{
If ((Arg2 == Zero))
{
Return (Buffer (0x02)
{
0x01, 0x08 // ..
})
}
If ((Arg2 == 0x0B))
{
BSTA = STAT /* \_SB_.NVDR.NVD2.STAT */
BHTH = HLTH /* \_SB_.NVDR.NVD2.HLTH */
BTMP = CTMP /* \_SB_.NVDR.NVD2.CTMP */
BETH = ETHS /* \_SB_.NVDR.NVD2.ETHS */
BWTH = WTHS /* \_SB_.NVDR.NVD2.WTHS */
BNLF = NVLF /* \_SB_.NVDR.NVD2.NVLF */
Return (SMRT) /* \_SB_.NVDR.NVD2.SMRT */
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
}
Device (NVD3)
{
Name (_ADR, 0x1330) // _ADR: Address
Name (SMRT, Buffer (0x0D)
{
0x00 // .
})
CreateDWordField (SMRT, Zero, BSTA)
CreateWordField (SMRT, 0x04, BHTH)
CreateWordField (SMRT, 0x06, BTMP)
CreateByteField (SMRT, 0x08, BETH)
CreateByteField (SMRT, 0x09, BWTH)
CreateByteField (SMRT, 0x0A, BNLF)
OperationRegion (BUF1, SystemMemory, 0xC0080000, 0x10)
Field (BUF1, DWordAcc, NoLock, Preserve)
{
STAT, 32,
HLTH, 16,
CTMP, 16,
ETHS, 8,
WTHS, 8,
NVLF, 8,
Offset (0x10)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05") /* Microsoft NVDIMM Command set */))
{
If ((Arg2 == Zero))
{
Return (Buffer (0x02)
{
0x01, 0x08 // ..
})
}
If ((Arg2 == 0x0B))
{
BSTA = STAT /* \_SB_.NVDR.NVD3.STAT */
BHTH = HLTH /* \_SB_.NVDR.NVD3.HLTH */
BTMP = CTMP /* \_SB_.NVDR.NVD3.CTMP */
BETH = ETHS /* \_SB_.NVDR.NVD3.ETHS */
BWTH = WTHS /* \_SB_.NVDR.NVD3.WTHS */
BNLF = NVLF /* \_SB_.NVDR.NVD3.NVLF */
Return (SMRT) /* \_SB_.NVDR.NVD3.SMRT */
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
}
Device (NVD4)
{
Name (_ADR, 0x1770) // _ADR: Address
Name (SMRT, Buffer (0x0D)
{
0x00 // .
})
CreateDWordField (SMRT, Zero, BSTA)
CreateWordField (SMRT, 0x04, BHTH)
CreateWordField (SMRT, 0x06, BTMP)
CreateByteField (SMRT, 0x08, BETH)
CreateByteField (SMRT, 0x09, BWTH)
CreateByteField (SMRT, 0x0A, BNLF)
OperationRegion (BUF1, SystemMemory, 0xC0088000, 0x10)
Field (BUF1, DWordAcc, NoLock, Preserve)
{
STAT, 32,
HLTH, 16,
CTMP, 16,
ETHS, 8,
WTHS, 8,
NVLF, 8,
Offset (0x10)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("1ee68b36-d4bd-4a1a-9a16-4f8e53d46e05") /* Microsoft NVDIMM Command set */))
{
If ((Arg2 == Zero))
{
Return (Buffer (0x02)
{
0x01, 0x08 // ..
})
}
If ((Arg2 == 0x0B))
{
BSTA = STAT /* \_SB_.NVDR.NVD4.STAT */
BHTH = HLTH /* \_SB_.NVDR.NVD4.HLTH */
BTMP = CTMP /* \_SB_.NVDR.NVD4.CTMP */
BETH = ETHS /* \_SB_.NVDR.NVD4.ETHS */
BWTH = WTHS /* \_SB_.NVDR.NVD4.WTHS */
BNLF = NVLF /* \_SB_.NVDR.NVD4.NVLF */
Return (SMRT) /* \_SB_.NVDR.NVD4.SMRT */
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
}
}
Device (TPM0)
{
Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
Name (_CID, "MSFT0101" /* TPM 2.0 Security Device */) // _CID: Compatible ID
Name (_UID, Zero) // _UID: Unique ID
Name (CRBB, 0x88500000)
Name (CRBL, 0x00100000)
Name (RBUF, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
0x88500000, // Address Base
0x00001000, // Address Length
_Y00)
})
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
CreateDWordField (RBUF, \_SB.TPM0._Y00._BAS, BASE) // _BAS: Base Address
CreateDWordField (RBUF, \_SB.TPM0._Y00._LEN, LENG) // _LEN: Length
BASE = CRBB /* \_SB_.TPM0.CRBB */
LENG = CRBL /* \_SB_.TPM0.CRBL */
Return (RBUF) /* \_SB_.TPM0.RBUF */
}
Method (_STR, 0, NotSerialized) // _STR: Description String
{
Return (Unicode ("TPM 2.0 Device"))
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
If (TPMF)
{
Return (0x0F)
}
Return (Zero)
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (0x02)
{
0xFF, 0x01 // ..
})
}
Case (One)
{
Return ("1.3")
}
Case (0x02)
{
Return (One)
}
Case (0x03)
{
Return (Package (0x02)
{
Zero,
Zero
})
}
Case (0x04)
{
Return (0x02)
}
Case (0x05)
{
Return (Package (0x03)
{
Zero,
Zero,
Zero
})
}
Case (0x06)
{
Return (0x03)
}
Case (0x07)
{
Return (One)
}
Case (0x08)
{
Return (0x04)
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
}
Device (LED)
{
Name (_HID, "AMPC0008") // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Altra LED Device")) // _STR: Description String
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"uuid",
Package (0x04)
{
0x5598273C,
0xA49611EA,
0xBB370242,
0xAC130002
}
}
}
})
}
Device (TAAD)
{
Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Name (_STR, Unicode ("Altra Time Device")) // _STR: Description String
OperationRegion (GRTC, SystemMemory, 0x00001000026D0000, 0x04)
Field (GRTC, DWordAcc, NoLock, Preserve)
{
RTCB, 32
}
Scope (^I2C6)
{
OperationRegion (TOP1, GenericSerialBus, 0x04, 0x0100)
Field (TOP1, BufferAcc, NoLock, Preserve)
{
Connection (
I2cSerialBusV2 (0x0051, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.I2C6",
0x00, ResourceConsumer, , Exclusive,
)
),
AccessAs (BufferAcc, AttribBytes (0x08)),
TBUF, 8
}
}
Name (BUFF, Buffer (0x0A){})
CreateByteField (BUFF, Zero, STAT)
CreateField (BUFF, 0x10, 0x40, DATA)
CreateByteField (BUFF, 0x08, HY)
CreateByteField (BUFF, 0x07, HM)
CreateByteField (BUFF, 0x05, HD)
CreateByteField (BUFF, 0x04, HH)
CreateByteField (BUFF, 0x03, HMI)
CreateByteField (BUFF, 0x02, HS)
Name (BUF2, Buffer (0x10){})
CreateWordField (BUF2, Zero, Y)
CreateByteField (BUF2, 0x02, M)
CreateByteField (BUF2, 0x03, D)
CreateByteField (BUF2, 0x04, H)
CreateByteField (BUF2, 0x05, MI)
CreateByteField (BUF2, 0x06, S)
CreateByteField (BUF2, 0x07, VA)
CreateByteField (BUF2, 0x0A, TZ)
CreateByteField (BUF2, 0x0C, DL)
Name (BRET, Buffer (0x07){})
CreateWordField (BRET, Zero, IY)
CreateByteField (BRET, 0x02, IM)
CreateByteField (BRET, 0x03, ID)
CreateByteField (BRET, 0x04, IH)
CreateByteField (BRET, 0x05, IMI)
CreateByteField (BRET, 0x06, IS)
Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities
{
Return (0x04)
}
Method (_GRT, 0, Serialized) // _GRT: Get Real Time
{
If ((^^I2C6.AVBL != One))
{
VA = Zero
Return (BUF2) /* \_SB_.TAAD.BUF2 */
}
Local0 = RTCB /* \_SB_.TAAD.RTCB */
Local1 = 0x000186A0
While (Local1)
{
If (((Local0 & 0x10) == 0x10))
{
Stall (0x64)
Local1 -= 0x64
}
Else
{
Break
}
Local0 = RTCB /* \_SB_.TAAD.RTCB */
}
If ((Local1 == Zero))
{
VA = Zero
Return (BUF2) /* \_SB_.TAAD.BUF2 */
}
BUFF = ^^I2C6.TBUF /* \_SB_.I2C6.TBUF */
Y = ((((HY & 0xF0) >> 0x04) * 0x0A) +
(HY & 0x0F))
Y += 0x07D0
If ((Y > 0x0833))
{
Y = 0x0833
}
If ((Y < 0x07D0))
{
Y = 0x07D0
}
M = ((((HM & 0x10) >> 0x04) * 0x0A) +
(HM & 0x0F))
D = ((((HD & 0x30) >> 0x04) * 0x0A) +
(HD & 0x0F))
H = ((((HH & 0x30) >> 0x04) * 0x0A) +
(HH & 0x0F))
MI = ((((HMI & 0x70) >> 0x04) * 0x0A) +
(HMI & 0x0F))
S = ((((HS & 0x70) >> 0x04) * 0x0A) +
(HS & 0x0F))
VA = One
TZ = Zero
DL = Zero
If ((STAT != Zero))
{
VA = Zero
}
Return (BUF2) /* \_SB_.TAAD.BUF2 */
}
Method (TTOE, 1, NotSerialized)
{
CreateWordField (Arg0, Zero, IY)
CreateByteField (Arg0, 0x02, IM)
CreateByteField (Arg0, 0x03, ID)
CreateByteField (Arg0, 0x04, IH)
CreateByteField (Arg0, 0x05, IMI)
CreateByteField (Arg0, 0x06, IS)
Local0 = ((0x0E - IM) / 0x0C)
Local1 = ((IY + 0x12C0) - Local0)
Local2 = ((IM + (0x0C * Local0)) - 0x03)
Local3 = (((((((ID + (((
0x99 * Local2) + 0x02) / 0x05)) + (0x016D * Local1)) +
(Local1 / 0x04)) - (Local1 / 0x64)) + (Local1 / 0x0190
)) - 0x7D2D) - 0x00253D8C)
Return (((Local3 * 0x00015180) + (((IH * 0x0E10) +
(IMI * 0x3C)) + IS)))
}
Method (ETOT, 1, NotSerialized)
{
Local0 = ((Arg0 / 0x00015180) + 0x00253D8C)
Local1 = (Local0 + 0x7D2C)
Divide (Local1, 0x00023AB1, Local3, Local2)
Local0 = ((((Local3 / 0x8EAC) + One) * 0x03) /
0x04)
Local1 = (Local3 - (Local0 * 0x8EAC))
Divide (Local1, 0x05B5, Local4, Local3)
Local1 = ((((Local4 / 0x016D) + One) * 0x03) /
0x04)
Local4 -= (Local1 * 0x016D)
Local0 = ((((Local2 * 0x0190) + (Local0 * 0x64)
) + (Local3 * 0x04)) + Local1)
Local2 = ((((Local4 * 0x05) + 0x0134) / 0x99) -
0x02)
Local4 = ((Local4 - (((Local2 + 0x04) * 0x99) /
0x05)) + 0x7A)
IY = ((Local0 - 0x12C0) + ((Local2 + 0x02) / 0x0C
))
IM = (((Local2 + 0x02) % 0x0C) + One)
ID = (Local4 + One)
IS = (Arg0 % 0x3C)
Local1 = ((Arg0 - IS) / 0x3C)
IMI = (Local1 % 0x3C)
IH = (((Local1 - IMI) / 0x3C) % 0x18)
}
Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time
{
CreateWordField (Arg0, 0x0A, ITZ)
CreateByteField (Arg0, 0x0C, IDL)
If ((^^I2C6.AVBL != One))
{
Return (Zero)
}
Local0 = RTCB /* \_SB_.TAAD.RTCB */
Local1 = 0x000186A0
While (Local1)
{
If (((Local0 & 0x10) == 0x10))
{
Stall (0x64)
Local1 -= 0x64
}
Else
{
Break
}
Local0 = RTCB /* \_SB_.TAAD.RTCB */
}
If ((Local1 == Zero))
{
Return (0xFFFFFFFF)
}
Local2 = TTOE (Arg0)
If ((ITZ != 0x07FF))
{
If ((ITZ < 0x8000))
{
Local2 += (ITZ * 0x3C)
}
Else
{
Local2 -= ((0x00010000 - ITZ) * 0x3C)
}
}
If (((IDL & 0x02) == 0x02))
{
Local2 -= 0x0E10
}
ETOT (Local2)
If ((IY > 0x0833))
{
IY = 0x0833
}
If ((IY < 0x07D0))
{
IY = 0x07D0
}
IY -= 0x07D0
HY = ((((IY / 0x0A) & 0x0F) << 0x04) |
((IY % 0x0A) & 0x0F))
HM = ((((IM / 0x0A) & One) << 0x04) |
((IM % 0x0A) & 0x0F))
HD = ((((ID / 0x0A) & 0x03) << 0x04) |
((ID % 0x0A) & 0x0F))
HH = ((((IH / 0x0A) & 0x03) << 0x04) |
((IH % 0x0A) & 0x0F))
HMI = ((((IMI / 0x0A) & 0x07) << 0x04) |
((IMI % 0x0A) & 0x0F))
HS = ((((IS / 0x0A) & 0x07) << 0x04) |
((IS % 0x0A) & 0x0F))
BUFF = ^^I2C6.TBUF = BUFF /* \_SB_.TAAD.BUFF */
If ((STAT != Zero))
{
Return (0xFFFFFFFF)
}
Return (Zero)
}
}
Scope (GED0)
{
Method (_EVT, 1, Serialized) // _EVT: Event
{
Switch (ToInteger (Arg0))
{
Case (0x54)
{
Notify (HED0, 0x80) // Status Change
}
Case (0x2C)
{
Local0 = (DOUT & 0x00FF0000)
If ((Local0 == 0x00010000))
{
Local0 = (STA4 & 0xFFFFFFFF)
If (Local0)
{
STA4 = Local0
}
Local0 = (A120 & 0xFF000000)
If ((Local0 == 0x01000000))
{
Notify (^^PCIA.P2P1, One) // Device Check
A120 = 0x02000201
}
Local0 = (A122 & 0xFF000000)
If ((Local0 == 0x01000000))
{
Notify (^^PCIA.P2P3, One) // Device Check
A122 = 0x02020201
}
}
ElseIf ((Local0 == Zero))
{
Local0 = (STA4 & 0xFFFFFFFF)
If (Local0)
{
STA4 = Local0
}
Local0 = (A120 & 0xFF000000)
If ((Local0 == Zero))
{
Notify (^^PCIA.P2P1, 0x03) // Eject Request
A120 = 0x02000201
}
Local0 = (A122 & 0xFF000000)
If ((Local0 == Zero))
{
Notify (^^PCIA.P2P3, 0x03) // Eject Request
A122 = 0x02020201
}
}
}
}
}
}
Device (PCI0)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x0C) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI0") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x80
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x81
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x82
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x83
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x80
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x81
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x82
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x83
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x80
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x81
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x82
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x83
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x80
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x81
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x82
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x83
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000033FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000040000000, // Range Minimum
0x000000004FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000300000000000, // Range Minimum
0x000033FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI0.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI1)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x0D) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI1") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 1 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x84
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x85
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x86
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x87
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x84
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x85
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x86
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x87
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x84
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x85
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x86
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x87
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x84
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x85
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x86
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x87
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000037FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000050000000, // Range Minimum
0x000000005FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000340000000000, // Range Minimum
0x000037FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI1._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI1._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI1._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI1.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI2)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, One) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI2") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 2 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x88
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x89
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x8A
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x8B
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x88
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x89
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x8A
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x8B
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x88
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x89
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x8A
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x8B
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x88
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x89
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x8A
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x8B
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00003BFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000030000000, // Range Minimum
0x0000000037FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000380000000000, // Range Minimum
0x00003BFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI2._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI2._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI2._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI2.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI3)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI3") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 3 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x8C
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x8D
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x8E
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x8F
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x8C
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x8D
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x8E
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x8F
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x8C
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x8D
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x8E
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x8F
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x8C
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x8D
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x8E
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x8F
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00003FFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000038000000, // Range Minimum
0x000000003FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00003C0000000000, // Range Minimum
0x00003FFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI3._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI3._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI3._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI3.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI4)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x02) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI4") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 4 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x93
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x90
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x91
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x92
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x93
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000023FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000001000000, // Range Minimum
0x0000000007FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000007000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000200000000000, // Range Minimum
0x000023FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI4._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI4._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI4.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI5)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x03) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI5") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 5 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x97
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x94
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x95
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x96
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x97
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000027FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000008000000, // Range Minimum
0x000000000FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000240000000000, // Range Minimum
0x000027FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI5._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI5._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI5.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI6)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x04) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI6") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 6 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x9B
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x98
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x99
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x9A
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x9B
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00002BFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000010000000, // Range Minimum
0x0000000017FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000280000000000, // Range Minimum
0x00002BFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI6._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI6._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI6.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCI7)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x05) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCI7") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 7 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x9F
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x9C
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x9D
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x9E
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x9F
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00002FFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000018000000, // Range Minimum
0x000000001FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00002C0000000000, // Range Minimum
0x00002FFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCI7._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCI7._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCI7._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCI7.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x00)
}
}
Device (PCIA)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x06) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCIA") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 10 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01C8
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01C9
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01CA
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01CB
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01C8
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01C9
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01CA
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01CB
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01C8
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01C9
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01CA
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01CB
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01C8
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01C9
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01CA
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01CB
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00007BFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000070000000, // Range Minimum
0x0000000077FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000780000000000, // Range Minimum
0x00007BFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCIA._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCIA._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCIA._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCIA.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
OperationRegion (DNS1, SystemMemory, 0x0000100000541010, 0x04)
Field (DNS1, DWordAcc, NoLock, Preserve)
{
OUTV, 32
}
Device (P2P1)
{
Name (_ADR, 0x00010000) // _ADR: Address
Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters
{
0x08,
0x40,
One,
Zero
})
Device (S0F0)
{
Name (_ADR, Zero) // _ADR: Address
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
OUTV = 0x68002021
}
Name (_SUN, One) // _SUN: Slot User Number
}
}
Device (P2P3)
{
Name (_ADR, 0x00030000) // _ADR: Address
Name (_HPP, Package (0x04) // _HPP: Hot Plug Parameters
{
0x08,
0x40,
One,
Zero
})
Device (S0F0)
{
Name (_ADR, Zero) // _ADR: Address
Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
{
OUTV = 0x68002221
}
Name (_SUN, 0x02) // _SUN: Slot User Number
}
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PCIB)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x00)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x07) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCIB") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 11 Device")) // _STR: Description String
Name (_PRT, Package (0x10) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01CC
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01CD
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01CE
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01CF
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01CC
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01CD
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01CE
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01CF
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01CC
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01CD
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01CE
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01CF
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01CC
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01CD
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01CE
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01CF
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00007FFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000078000000, // Range Minimum
0x000000007FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00007C0000000000, // Range Minimum
0x00007FFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCIB._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCIB._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCIB._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCIB.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PCIC)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x08) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCIC") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 12 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x01D3
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x01D0
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x01D1
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x01D2
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x01D3
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000063FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000040000000, // Range Minimum
0x0000000047FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000600000000000, // Range Minimum
0x000063FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCIC._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCIC._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCIC._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCIC.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PCID)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x09) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCID") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 13 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x01D7
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x01D4
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x01D5
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x01D6
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x01D7
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x000067FFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000048000000, // Range Minimum
0x000000004FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000640000000000, // Range Minimum
0x000067FFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCID._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCID._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCID._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCID.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PCIE)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x0A) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCIE") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 14 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x01DB
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x01D8
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x01D9
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x01DA
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x01DB
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00006BFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000050000000, // Range Minimum
0x0000000057FFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000680000000000, // Range Minimum
0x00006BFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCIE._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCIE._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCIE._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCIE.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PCIF)
{
Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
Name (_CCA, One) // _CCA: Cache Coherency Attribute
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, 0x0B) // _SEG: PCI Segment
Name (_BBN, Zero) // _BBN: BIOS Bus Number
Name (_UID, "PCIF") // _UID: Unique ID
Name (_STR, Unicode ("PCIe 15 Device")) // _STR: Description String
Name (_PRT, Package (0x20) // _PRT: PCI Routing Table
{
Package (0x04)
{
0x0001FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0001FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0001FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0001FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0002FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0002FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0002FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0003FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0003FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0003FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0004FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0004FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0004FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0004FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0005FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0005FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0005FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0005FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0006FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0006FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0006FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0006FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0007FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0007FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0007FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0007FFFF,
0x03,
Zero,
0x01DF
},
Package (0x04)
{
0x0008FFFF,
Zero,
Zero,
0x01DC
},
Package (0x04)
{
0x0008FFFF,
One,
Zero,
0x01DD
},
Package (0x04)
{
0x0008FFFF,
0x02,
Zero,
0x01DE
},
Package (0x04)
{
0x0008FFFF,
0x03,
Zero,
0x01DF
}
})
Method (_CBA, 0, Serialized) // _CBA: Configuration Base Address
{
Return (0x00006FFFF0000000)
}
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Name (RBUF, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x0000, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0100, // Length
,, )
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000000058000000, // Range Minimum
0x000000005FFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000008000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00006C0000000000, // Range Minimum
0x00006FFFDFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x000003FFE0000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Return (RBUF) /* \_SB_.PCIF._CRS.RBUF */
}
Name (SUPP, Zero)
Name (CTRL, Zero)
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, CDW1)
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
CreateDWordField (Arg3, 0x04, CDW2)
CreateDWordField (Arg3, 0x08, CDW3)
SUPP = CDW2 /* \_SB_.PCIF._OSC.CDW2 */
CTRL = CDW3 /* \_SB_.PCIF._OSC.CDW3 */
If (((SUPP & 0x16) != 0x16))
{
CTRL &= 0x1E
}
CTRL &= 0x18
If ((Arg1 != One))
{
CDW1 |= 0x08
}
If ((CDW3 != CTRL))
{
CDW1 |= 0x10
}
CDW3 = CTRL /* \_SB_.PCIF.CTRL */
Return (Arg3)
}
Else
{
CDW1 |= 0x04
Return (Arg3)
}
}
Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
{
If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
{
Switch (ToInteger (Arg2))
{
Case (Zero)
{
Return (Buffer (One)
{
0x01 // .
})
}
}
}
Return (Buffer (One)
{
0x00 // .
})
}
Device (RP0)
{
Name (_ADR, Zero) // _ADR: Address
}
Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
{
Return (0x01)
}
}
Device (PDRC)
{
Name (_HID, EisaId ("PNP0C02") /* PNP Motherboard Resources */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Name (PDRS, ResourceTemplate ()
{
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00003BFFF0000000, // Range Minimum
0x00003BFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00003FFFF0000000, // Range Minimum
0x00003FFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000023FFF0000000, // Range Minimum
0x000023FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000027FFF0000000, // Range Minimum
0x000027FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00002BFFF0000000, // Range Minimum
0x00002BFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00002FFFF0000000, // Range Minimum
0x00002FFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00007BFFF0000000, // Range Minimum
0x00007BFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00007FFFF0000000, // Range Minimum
0x00007FFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000063FFF0000000, // Range Minimum
0x000063FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000067FFF0000000, // Range Minimum
0x000067FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00006BFFF0000000, // Range Minimum
0x00006BFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x00006FFFF0000000, // Range Minimum
0x00006FFFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000033FFF0000000, // Range Minimum
0x000033FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
0x0000000000000000, // Granularity
0x000037FFF0000000, // Range Minimum
0x000037FFFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000000010000000, // Length
,, , AddressRangeMemory, TypeStatic)
})
Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
{
Return (PDRS) /* \_SB_.PDRC.PDRS */
}
}
}
Scope (_SB)
{
Name (CPCE, One)
Name (LPIE, One)
Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities
{
CreateDWordField (Arg3, Zero, STS0)
CreateDWordField (Arg3, 0x04, CAP0)
If ((Arg0 == ToUUID ("0811b06e-4a27-44f9-8d60-3cbbc22e7b48") /* Platform-wide Capabilities */))
{
If ((Arg1 != One))
{
STS0 &= 0xFFFFFFE0
STS0 |= 0x0A
}
Else
{
If (((CAP0 & 0x0100) == 0x0100))
{
CAP0 &= 0xFFFFFEFF
STS0 &= 0xFFFFFFE0
STS0 |= 0x12
}
If ((LPIE == One))
{
CAP0 |= 0x80
}
Else
{
CAP0 &= 0xFFFFFF7F
}
If ((CPCE == One))
{
CAP0 |= 0x40
}
Else
{
CAP0 &= 0xFFFFFFBF
}
}
}
Else
{
STS0 &= 0xFFFFFFE0
STS0 |= 0x06
}
Return (Arg3)
}
Name (CLPI, Package (0x04)
{
Zero,
One,
One,
Package (0x0A)
{
One,
One,
One,
Zero,
Zero,
One,
0x01000000,
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
"Standby"
}
})
Name (PLPI, Package (0x05)
{
Zero,
0x02,
0x02,
Package (0x0A)
{
One,
One,
One,
Zero,
Zero,
Zero,
ResourceTemplate ()
{
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000FFFFFFFF, // Address
0x03, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
"WFI"
},
Package (0x0A)
{
One,
0x0B54,
One,
Zero,
Zero,
One,
ResourceTemplate ()
{
Register (FFixedHW,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000001, // Address
0x03, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
"Standby"
}
})
Device (SYST)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_LPI, Package (0x04) // _LPI: Low Power Idle States
{
Zero,
Zero,
One,
Package (0x0A)
{
0x64,
0x63,
One,
Zero,
0x64,
Zero,
0x01000100,
ResourceTemplate ()
{
Register (SystemMemory,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000088980000, // Address
0x04, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000088980008, // Address
0x03, // Access Size
)
},
"System Standby"
}
})
}
}
Scope (_SB.SYST)
{
Device (CL00)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL01)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL02)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x03) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL03)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x04) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL04)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x05) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL05)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x06) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL06)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x07) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL07)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x08) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL08)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x09) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL09)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0A) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0A)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0B) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0B)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0C) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0C)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0D) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0D)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0E) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0E)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x0F) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL0F)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x10) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL10)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x11) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL11)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x12) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL12)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x13) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL13)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x14) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL14)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x15) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL15)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x16) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL16)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x17) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL17)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x18) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL18)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x19) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL19)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1A) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1A)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1B) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1B)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1C) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1C)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1D) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1D)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1E) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1E)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x1F) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL1F)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x20) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL20)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x21) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL21)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x22) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL22)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x23) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL23)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x24) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL24)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x25) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL25)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x26) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL26)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x27) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL27)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x28) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL28)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x29) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL29)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2A) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2A)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2B) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2B)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2C) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2C)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2D) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2D)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2E) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2E)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x2F) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL2F)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x30) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL30)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x31) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL31)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x32) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL32)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x33) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL33)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x34) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL34)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x35) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL35)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x36) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL36)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x37) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL37)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x38) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL38)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x39) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL39)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3A) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3A)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3B) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3B)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3C) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3C)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3D) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3D)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3E) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3E)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x3F) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
Device (CL3F)
{
Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
Name (_UID, 0x40) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (CLPI) /* \_SB_.CLPI */
}
}
}
Scope (_SB.SYST.CL00)
{
Device (C000)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000004, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000008, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000000C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000010, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000014, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000002C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000034, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000003C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000050, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000054, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000058, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL00.C000.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
Zero,
0xFD,
0x02
}
})
}
Device (C001)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000080, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000084, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000088, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000008C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000090, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000094, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000000AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000000B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000000BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000000D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000000D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000000D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL00.C001.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
One,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL01)
{
Device (C002)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0100) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000100, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000104, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000108, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000010C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000110, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000114, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000012C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000134, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000013C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000150, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000154, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000158, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL01.C002.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x02,
0xFD,
0x02
}
})
}
Device (C003)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0101) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000180, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000184, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000188, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000018C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000190, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000194, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000001AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000001B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000001BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000001D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000001D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000001D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL01.C003.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x03,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL02)
{
Device (C004)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0200) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000200, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000204, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000208, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000020C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000210, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000214, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000022C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000234, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000023C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000250, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000254, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000258, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL02.C004.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x04,
0xFD,
0x02
}
})
}
Device (C005)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0201) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000280, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000284, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000288, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000028C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000290, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000294, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000002AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000002B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000002BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000002D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000002D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000002D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL02.C005.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x05,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL03)
{
Device (C006)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0300) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000300, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000304, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000308, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000030C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000310, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000314, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000032C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000334, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000033C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000350, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000354, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000358, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL03.C006.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x06,
0xFD,
0x02
}
})
}
Device (C007)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0301) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000380, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000384, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000388, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000038C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000390, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000394, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000003AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000003B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000003BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000003D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000003D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000003D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL03.C007.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x07,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL04)
{
Device (C008)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0400) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000400, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000404, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000408, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000040C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000410, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000414, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000042C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000434, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000043C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000450, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000454, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000458, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL04.C008.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x08,
0xFD,
0x02
}
})
}
Device (C009)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0401) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000480, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000484, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000488, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000048C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000490, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000494, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000004AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000004B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000004BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000004D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000004D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000004D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL04.C009.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x09,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL05)
{
Device (C010)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0500) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000500, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000504, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000508, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000050C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000510, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000514, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000052C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000534, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000053C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000550, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000554, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000558, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL05.C010.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0A,
0xFD,
0x02
}
})
}
Device (C011)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0501) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000580, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000584, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000588, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000058C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000590, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000594, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000005AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000005B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000005BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000005D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000005D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000005D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL05.C011.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0B,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL06)
{
Device (C012)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0600) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000600, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000604, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000608, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000060C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000610, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000614, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000062C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000634, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000063C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000650, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000654, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000658, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL06.C012.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0C,
0xFD,
0x02
}
})
}
Device (C013)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0601) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000680, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000684, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000688, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000068C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000690, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000694, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000006AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000006B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000006BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000006D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000006D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000006D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL06.C013.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0D,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL07)
{
Device (C014)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0700) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000700, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000704, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000708, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000070C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000710, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000714, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000072C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000734, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000073C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000750, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000754, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000758, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL07.C014.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0E,
0xFD,
0x02
}
})
}
Device (C015)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0701) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000780, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000784, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000788, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000078C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000790, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000794, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000007AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000007B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000007BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000007D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000007D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000007D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL07.C015.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x0F,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL08)
{
Device (C016)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0800) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000800, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000804, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000808, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000080C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000810, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000814, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000082C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000834, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000083C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000850, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000854, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000858, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL08.C016.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x10,
0xFD,
0x02
}
})
}
Device (C017)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0801) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000880, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000884, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000888, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000088C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000890, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000894, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000008AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000008B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000008BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000008D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000008D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000008D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL08.C017.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x11,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL09)
{
Device (C018)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0900) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000900, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000904, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000908, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000090C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000910, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000914, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x000000000000092C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000934, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000093C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000950, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000954, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000958, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL09.C018.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x12,
0xFD,
0x02
}
})
}
Device (C019)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0901) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000980, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000984, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000988, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x000000000000098C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000990, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000994, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000009AC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x00000000000009B4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000009BC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000009D0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000009D4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x00000000000009D8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL09.C019.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x13,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL0A)
{
Device (C020)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0A00) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A00, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A04, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A08, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A0C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A10, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A14, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000A2C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000A34, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A3C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A50, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A54, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A58, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0A.C020.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x14,
0xFD,
0x02
}
})
}
Device (C021)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0A01) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A80, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A84, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A88, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A8C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A90, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000A94, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000AAC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000AB4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000ABC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000AD0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000AD4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000AD8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0A.C021.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x15,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL0B)
{
Device (C022)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0B00) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B00, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B04, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B08, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B0C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B10, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B14, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000B2C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000B34, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B3C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B50, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B54, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B58, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0B.C022.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x16,
0xFD,
0x02
}
})
}
Device (C023)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0B01) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B80, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B84, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B88, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B8C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B90, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000B94, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000BAC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000BB4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000BBC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000BD0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000BD4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000BD8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0B.C023.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x17,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL0C)
{
Device (C024)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0C00) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C00, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C04, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C08, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C0C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C10, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C14, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000C2C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000C34, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C3C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C50, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C54, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C58, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0C.C024.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x18,
0xFD,
0x02
}
})
}
Device (C025)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0C01) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C80, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C84, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C88, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C8C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C90, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000C94, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000CAC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000CB4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000CBC, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000CD0, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000CD4, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000CD8, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0C.C025.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x19,
0xFD,
0x02
}
})
}
}
Scope (_SB.SYST.CL0D)
{
Device (C026)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0D00) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D00, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D04, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D08, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D0C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D10, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D14, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000D2C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x40, // Bit Width
0x00, // Bit Offset
0x0000000000000D34, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D3C, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (SystemMemory,
0x00, // Bit Width
0x00, // Bit Offset
0x0000000000000000, // Address
,)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D50, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D54, // Address
0x02, // Access Size
)
},
ResourceTemplate ()
{
Register (PCC,
0x20, // Bit Width
0x00, // Bit Offset
0x0000000000000D58, // Address
0x02, // Access Size
)
}
})
If ((CPCE == One))
{
Method (_CPC, 0, NotSerialized) // _CPC: Continuous Performance Control
{
Return (PCPC) /* \_SB_.SYST.CL0D.C026.PCPC */
}
}
Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
{
Package (0x05)
{
0x05,
Zero,
0x1A,
0xFD,
0x02
}
})
}
Device (C027)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x0D01) // _UID: Unique ID
Method (_LPI, 0, NotSerialized) // _LPI: Low Power Idle States
{
Return (PLPI) /* \_SB_.PLPI */
}
Name (PCPC, Package (0x17)
{
0x17,
0x03,
ResourceTemplate ()
{
Register (PCC,
0x20,