Skip to content

Commit

Permalink
Merge pull request #74 from slaclab/pre-release
Browse files Browse the repository at this point in the history 
Release Candidate v3.7.0
  • Loading branch information
@ruck314
ruck314 authored Jul 6, 2021
2 parents 548d0af + 1decbfc commit 2d1f428
Show file tree
Hide file tree
Showing 4 changed files with 207 additions and 49 deletions.
238 changes: 190 additions & 48 deletions hardware/XilinxKcu1500/rtl/XilinxKcu1500Core.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,12 +19,13 @@ use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


library surf;
use surf.StdRtlPkg.all;
use surf.AxiLitePkg.all;
use surf.AxiStreamPkg.all;
use surf.AxiPkg.all;
use surf.I2cPkg.all;
use surf.I2cMuxPkg.all;

library axi_pcie_core;
use axi_pcie_core.AxiPciePkg.all;
Expand All @@ -47,67 +48,86 @@ entity XilinxKcu1500Core is
------------------------
-- Top Level Interfaces
------------------------
userClk156 : out sl;
userClk156 : out sl;
-- DMA Interfaces (dmaClk domain)
dmaClk : out sl;
dmaRst : out sl;
dmaBuffGrpPause : out slv(7 downto 0);
dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaClk : out sl;
dmaRst : out sl;
dmaBuffGrpPause : out slv(7 downto 0);
dmaObMasters : out AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaObSlaves : in AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
dmaIbMasters : in AxiStreamMasterArray(DMA_SIZE_G-1 downto 0);
dmaIbSlaves : out AxiStreamSlaveArray(DMA_SIZE_G-1 downto 0);
-- PIP Interface [0x00080000:0009FFFF] (dmaClk domain)
pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipIbMaster : out AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipIbSlave : in AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
pipObMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
pipObSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
-- User General Purpose AXI4 Interfaces (dmaClk domain)
usrReadMaster : in AxiReadMasterType := AXI_READ_MASTER_INIT_C;
usrReadSlave : out AxiReadSlaveType := AXI_READ_SLAVE_FORCE_C;
usrWriteMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
usrWriteSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
usrReadMaster : in AxiReadMasterType := AXI_READ_MASTER_INIT_C;
usrReadSlave : out AxiReadSlaveType := AXI_READ_SLAVE_FORCE_C;
usrWriteMaster : in AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
usrWriteSlave : out AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;
-- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF] (appClk domain)
appClk : in sl := '0';
appRst : in sl := '1';
appReadMaster : out AxiLiteReadMasterType;
appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C;
appWriteMaster : out AxiLiteWriteMasterType;
appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C;
appClk : in sl := '0';
appRst : in sl := '1';
appReadMaster : out AxiLiteReadMasterType;
appReadSlave : in AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_OK_C;
appWriteMaster : out AxiLiteWriteMasterType;
appWriteSlave : in AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_OK_C;
-------------------
-- Top Level Ports
-------------------
-- System Ports
emcClk : in sl;
userClkP : in sl;
userClkN : in sl;
emcClk : in sl;
userClkP : in sl;
userClkN : in sl;
i2cRstL : out sl;
i2cScl : inout sl;
i2cSda : inout sl;
-- QSFP[0] Ports
qsfp0RstL : out sl;
qsfp0LpMode : out sl;
qsfp0ModSelL : out sl;
qsfp0ModPrsL : in sl := '0';
qsfp0RstL : out sl;
qsfp0LpMode : out sl;
qsfp0ModSelL : out sl;
qsfp0ModPrsL : in sl := '0';
-- QSFP[1] Ports
qsfp1RstL : out sl;
qsfp1LpMode : out sl;
qsfp1ModSelL : out sl;
qsfp1ModPrsL : in sl := '0';
qsfp1RstL : out sl;
qsfp1LpMode : out sl;
qsfp1ModSelL : out sl;
qsfp1ModPrsL : in sl := '0';
-- Boot Memory Ports
flashCsL : out sl;
flashMosi : out sl;
flashMiso : in sl;
flashHoldL : out sl;
flashWp : out sl;
flashCsL : out sl;
flashMosi : out sl;
flashMiso : in sl;
flashHoldL : out sl;
flashWp : out sl;
-- PCIe Ports
pciRstL : in sl;
pciRefClkP : in sl;
pciRefClkN : in sl;
pciRxP : in slv(7 downto 0);
pciRxN : in slv(7 downto 0);
pciTxP : out slv(7 downto 0);
pciTxN : out slv(7 downto 0));
pciRstL : in sl;
pciRefClkP : in sl;
pciRefClkN : in sl;
pciRxP : in slv(7 downto 0);
pciRxN : in slv(7 downto 0);
pciTxP : out slv(7 downto 0);
pciTxN : out slv(7 downto 0));
end XilinxKcu1500Core;

architecture mapping of XilinxKcu1500Core is

constant XBAR_I2C_CONFIG_C : AxiLiteCrossbarMasterConfigArray(5 downto 0) := genAxiLiteConfig(6, x"0007_0000", 16, 12);

constant SFF8472_I2C_CONFIG_C : I2cAxiLiteDevArray(1 downto 0) := (
0 => MakeI2cAxiLiteDevType(
i2cAddress => "1010000", -- 2 wire address 1010000X (A0h)
dataSize => 8, -- in units of bits
addrSize => 8, -- in units of bits
endianness => '0', -- Little endian
repeatStart => '1'), -- No repeat start
1 => MakeI2cAxiLiteDevType(
i2cAddress => "1010001", -- 2 wire address 1010001X (A2h)
dataSize => 8, -- in units of bits
addrSize => 8, -- in units of bits
endianness => '0', -- Little endian
repeatStart => '1')); -- Repeat Start

signal dmaReadMaster : AxiReadMasterType;
signal dmaReadSlave : AxiReadSlaveType;
signal dmaWriteMaster : AxiWriteMasterType;
Expand All @@ -133,6 +153,26 @@ architecture mapping of XilinxKcu1500Core is
signal intPipObMaster : AxiWriteMasterType := AXI_WRITE_MASTER_INIT_C;
signal intPipObSlave : AxiWriteSlaveType := AXI_WRITE_SLAVE_FORCE_C;

signal i2cReadMaster : AxiLiteReadMasterType;
signal i2cReadSlave : AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C;
signal i2cWriteMaster : AxiLiteWriteMasterType;
signal i2cWriteSlave : AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C;

signal i2cReadMasters : AxiLiteReadMasterArray(5 downto 0);
signal i2cReadSlaves : AxiLiteReadSlaveArray(5 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_DECERR_C);
signal i2cWriteMasters : AxiLiteWriteMasterArray(5 downto 0);
signal i2cWriteSlaves : AxiLiteWriteSlaveArray(5 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C);

signal i2ci : i2c_in_type;
signal i2coVec : i2c_out_array(6 downto 0) := (
others => (
scl => '1',
scloen => '1',
sda => '1',
sdaoen => '1',
enable => '0'));
signal i2co : i2c_out_type;

signal sysClock : sl;
signal sysReset : sl;
signal systemReset : sl;
Expand Down Expand Up @@ -171,12 +211,13 @@ begin
IB => userClkN,
O => userClk156);

i2cRstL <= not(systemReset);
qsfp0RstL <= not(systemReset);
qsfp1RstL <= not(systemReset);
qsfp0LpMode <= '0';
qsfp1LpMode <= '0';
qsfp0ModSelL <= '1';
qsfp1ModSelL <= '1';
qsfp0ModSelL <= '0';
qsfp1ModSelL <= '0';

---------------
-- AXI PCIe PHY
Expand Down Expand Up @@ -219,6 +260,102 @@ begin
pipIbMaster <= intPipIbMaster;
intPipIbSlave <= pipIbSlave;

U_XbarI2cMux : entity surf.AxiLiteCrossbarI2cMux
generic map (
TPD_G => TPD_G,
-- I2C MUX Generics
MUX_DECODE_MAP_G => I2C_MUX_DECODE_MAP_TCA9548_C,
I2C_MUX_ADDR_G => b"1110_100",
I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
AXIL_CLK_FREQ_G => DMA_CLK_FREQ_C,
-- AXI-Lite Crossbar Generics
NUM_MASTER_SLOTS_G => 6,
MASTERS_CONFIG_G => XBAR_I2C_CONFIG_C)
port map (
-- Clocks and Resets
axilClk => sysClock,
axilRst => sysReset,
-- Slave AXI-Lite Interface
sAxilWriteMaster => i2cWriteMaster,
sAxilWriteSlave => i2cWriteSlave,
sAxilReadMaster => i2cReadMaster,
sAxilReadSlave => i2cReadSlave,
-- Master AXI-Lite Interfaces
mAxilWriteMasters => i2cWriteMasters,
mAxilWriteSlaves => i2cWriteSlaves,
mAxilReadMasters => i2cReadMasters,
mAxilReadSlaves => i2cReadSlaves,
-- I2C MUX Ports
i2ci => i2ci,
i2co => i2coVec(6));

U_QSFP1 : entity surf.AxiI2cRegMasterCore
generic map (
TPD_G => TPD_G,
I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
DEVICE_MAP_G => SFF8472_I2C_CONFIG_C,
AXI_CLK_FREQ_G => DMA_CLK_FREQ_C)
port map (
-- I2C Ports
i2ci => i2ci,
i2co => i2coVec(1),
-- AXI-Lite Register Interface
axiReadMaster => i2cReadMasters(1),
axiReadSlave => i2cReadSlaves(1),
axiWriteMaster => i2cWriteMasters(1),
axiWriteSlave => i2cWriteSlaves(1),
-- Clocks and Resets
axiClk => sysClock,
axiRst => sysReset);

U_QSFP0 : entity surf.AxiI2cRegMasterCore
generic map (
TPD_G => TPD_G,
I2C_SCL_FREQ_G => 400.0E+3, -- units of Hz
DEVICE_MAP_G => SFF8472_I2C_CONFIG_C,
AXI_CLK_FREQ_G => DMA_CLK_FREQ_C)
port map (
-- I2C Ports
i2ci => i2ci,
i2co => i2coVec(4),
-- AXI-Lite Register Interface
axiReadMaster => i2cReadMasters(4),
axiReadSlave => i2cReadSlaves(4),
axiWriteMaster => i2cWriteMasters(4),
axiWriteSlave => i2cWriteSlaves(4),
-- Clocks and Resets
axiClk => sysClock,
axiRst => sysReset);

process(i2cReadMasters, i2cWriteMasters, i2coVec)
variable tmp : i2c_out_type;
begin
-- Init
tmp := i2coVec(6);
-- Check for TXN after XBAR/I2C_MUX
for i in 0 to 5 loop
if (i2cWriteMasters(i).awvalid = '1') or (i2cReadMasters(i).arvalid = '1') then
tmp := i2coVec(i);
end if;
end loop;
-- Return result
i2co <= tmp;
end process;

IOBUF_SCL : IOBUF
port map (
O => i2ci.scl,
IO => i2cScl,
I => i2co.scl,
T => i2co.scloen);

IOBUF_SDA : IOBUF
port map (
O => i2ci.sda,
IO => i2cSda,
I => i2co.sda,
T => i2co.sdaoen);

end generate;

SIM_PCIE : if (ROGUE_SIM_EN_G) generate
Expand Down Expand Up @@ -273,6 +410,11 @@ begin
phyReadSlave => phyReadSlave,
phyWriteMaster => phyWriteMaster,
phyWriteSlave => phyWriteSlave,
-- I2C AXI-Lite Interfaces (axiClk domain)
i2cReadMaster => i2cReadMaster,
i2cReadSlave => i2cReadSlave,
i2cWriteMaster => i2cWriteMaster,
i2cWriteSlave => i2cWriteSlave,
-- (Optional) Application AXI-Lite Interfaces
appClk => appClk,
appRst => appRst,
Expand Down
4 changes: 4 additions & 0 deletions hardware/XilinxKcu1500/xdc/XilinxKcu1500Core.xdc
View file
Original file line number Diff line number Diff line change
Expand Up @@ -72,6 +72,10 @@ set_property -dict { PACKAGE_PIN AR26 IOSTANDARD LVCMOS18 } [get_ports {pciRstL}
set_property -dict { PACKAGE_PIN AV24 IOSTANDARD LVDS_25 } [get_ports { userClkP }]; # 156.25 MHz
set_property -dict { PACKAGE_PIN AW24 IOSTANDARD LVDS_25 } [get_ports { userClkN }]; # 156.25 MHz

set_property -dict { PACKAGE_PIN AL24 IOSTANDARD LVCMOS18 } [get_ports { i2cRstL }];
set_property -dict { PACKAGE_PIN AN24 IOSTANDARD LVCMOS18 } [get_ports { i2cScl }];
set_property -dict { PACKAGE_PIN AP24 IOSTANDARD LVCMOS18 } [get_ports { i2cSda }];

##########################################
# QSFP[0] ports located in the core area #
##########################################
Expand Down
12 changes: 12 additions & 0 deletions python/axipcie/_AxiPcieCore.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,18 @@ def __init__(self,
enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
))

elif boardType == 'Kcu1500':

qsfpOffset = [0x74_000,0x71_000]

for i in range(2):
self.add(xceiver.Qsfp(
name = f'Qsfp[{i}]',
offset = qsfpOffset[i],
memBase = self.AxilBridge.proxy,
enabled = False, # enabled=False because I2C are slow transactions and might "log jam" register transaction pipeline
))

def _start(self):
super()._start()
DMA_SIZE_G = self.AxiVersion.DMA_SIZE_G.get()
Expand Down
2 changes: 1 addition & 1 deletion shared/ruckus.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
# Check for submodule tagging
if { [info exists ::env(OVERRIDE_SUBMODULE_LOCKS)] != 1 || $::env(OVERRIDE_SUBMODULE_LOCKS) == 0 } {
if { [SubmoduleCheck {ruckus} {2.6.0} ] < 0 } {exit -1}
if { [SubmoduleCheck {surf} {2.20.0} ] < 0 } {exit -1}
if { [SubmoduleCheck {surf} {2.21.0} ] < 0 } {exit -1}
} else {
puts "\n\n*********************************************************"
puts "OVERRIDE_SUBMODULE_LOCKS != 0"
Expand Down

0 comments on commit 2d1f428

Please sign in to comment.