Merge pull request #45 from slaclab/pre-release

v3.0.0 release candidate
slaclab · Nov 21, 2019 · 333ed1a · 333ed1a
2 parents 98b2ac3 + 89f565a
commit 333ed1a
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Showing 109 changed files with 980 additions and 553 deletions.
diff --git a/hardware/AlphaDataKu3/pcie/rtl/AlphaDataKu3PciePhyWrapper.vhd b/hardware/AlphaDataKu3/pcie/rtl/AlphaDataKu3PciePhyWrapper.vhd
@@ -16,10 +16,14 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiPciePkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
+use surf.AxiLitePkg.all;
+
+library axi_pcie_core;
+use axi_pcie_core.AxiPciePkg.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -178,7 +182,7 @@ architecture mapping of AlphaDataKu3PciePhyWrapper is
 begin
 
    axiClk <= clk;
-   U_Rst : entity work.RstPipeline
+   U_Rst : entity surf.RstPipeline
       generic map (
          TPD_G     => TPD_G,
          INV_RST_G => true)

diff --git a/hardware/AlphaDataKu3/pcie/ruckus.tcl b/hardware/AlphaDataKu3/pcie/ruckus.tcl
@@ -2,10 +2,10 @@
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
 # Load local Source Code and Constraints
-loadSource      -dir  "$::DIR_PATH/rtl"
+loadSource -lib axi_pcie_core  -dir  "$::DIR_PATH/rtl"
 
 # loadIpCore -path "$::DIR_PATH/ip/AlphaDataKu3PciePhy.xci"
-loadSource   -path "$::DIR_PATH/ip/AlphaDataKu3PciePhy.dcp"
+loadSource -lib axi_pcie_core -path "$::DIR_PATH/ip/AlphaDataKu3PciePhy.dcp"
 
 loadConstraints -path "$::DIR_PATH/ip/AlphaDataKu3PciePhy.xdc"
 set_property PROCESSING_ORDER {EARLY}                         [get_files {AlphaDataKu3PciePhy.xdc}]

diff --git a/hardware/AlphaDataKu3/rtl/AlphaDataKu3Core.vhd b/hardware/AlphaDataKu3/rtl/AlphaDataKu3Core.vhd
@@ -34,11 +34,15 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiStreamPkg.all;
-use work.AxiPkg.all;
-use work.AxiPciePkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+use surf.AxiStreamPkg.all;
+use surf.AxiPkg.all;
+
+library axi_pcie_core;
+use axi_pcie_core.AxiPciePkg.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -122,7 +126,7 @@ begin
 
    dmaClk <= sysClock;
 
-   U_Rst : entity work.RstPipeline
+   U_Rst : entity surf.RstPipeline
       generic map (
          TPD_G => TPD_G)
       port map (
@@ -141,7 +145,7 @@ begin
    -- AXI PCIe PHY
    ---------------   
    REAL_PCIE : if (not ROGUE_SIM_EN_G) generate
-      U_AxiPciePhy : entity work.AlphaDataKu3PciePhyWrapper
+      U_AxiPciePhy : entity axi_pcie_core.AlphaDataKu3PciePhyWrapper
          generic map (
             TPD_G => TPD_G)
          port map (
@@ -172,7 +176,7 @@ begin
             pciTxN         => pciTxN);
    end generate;
    SIM_PCIE : if (ROGUE_SIM_EN_G) generate
-      U_sysClock : entity work.ClkRst
+      U_sysClock : entity surf.ClkRst
          generic map (
             CLK_PERIOD_G      => 4 ns,  -- 250 MHz
             RST_START_DELAY_G => 0 ns,
@@ -185,7 +189,7 @@ begin
    ---------------
    -- AXI PCIe REG
    --------------- 
-   U_REG : entity work.AxiPcieReg
+   U_REG : entity axi_pcie_core.AxiPcieReg
       generic map (
          TPD_G                => TPD_G,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
@@ -228,7 +232,7 @@ begin
    ---------------
    -- AXI PCIe DMA
    ---------------   
-   U_AxiPcieDma : entity work.AxiPcieDma
+   U_AxiPcieDma : entity axi_pcie_core.AxiPcieDma
       generic map (
          TPD_G                => TPD_G,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,

diff --git a/hardware/AlphaDataKu3/rtl/AxiPciePkg.vhd b/hardware/AlphaDataKu3/rtl/AxiPciePkg.vhd
@@ -16,10 +16,12 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiStreamPkg.all;
-use work.AxiPkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+use surf.AxiStreamPkg.all;
+use surf.AxiPkg.all;
 
 package AxiPciePkg is
 

diff --git a/hardware/AlphaDataKu3/rtl/TerminateQsfp.vhd b/hardware/AlphaDataKu3/rtl/TerminateQsfp.vhd
@@ -18,7 +18,9 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-use work.StdRtlPkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -58,7 +60,7 @@ architecture mapping of TerminateQsfp is
 begin
 
    -- Unused QSFP Port
-   U_QSFP0 : entity work.Gthe3ChannelDummy
+   U_QSFP0 : entity surf.Gthe3ChannelDummy
       generic map (
          TPD_G   => TPD_G,
          WIDTH_G => 4)
@@ -70,7 +72,7 @@ begin
          gtTxN  => qsfp0TxN);
 
    -- Unused QSFP Port
-   U_QSFP1 : entity work.Gthe3ChannelDummy
+   U_QSFP1 : entity surf.Gthe3ChannelDummy
       generic map (
          TPD_G   => TPD_G,
          WIDTH_G => 4)

diff --git a/hardware/AlphaDataKu3/ruckus.tcl b/hardware/AlphaDataKu3/ruckus.tcl
@@ -16,7 +16,7 @@ if { $::env(PRJ_PART) != "XCKU060-FFVA1156-2-E" } {
 set_property board_part alpha-data.com:adm-pcie3-ku3:part0:1.0 [current_project]
 
 # Load local Source Code and Constraints
-loadSource      -dir  "$::DIR_PATH/rtl"
+loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl"
 loadConstraints -path "$::DIR_PATH/xdc/AlphaDataKu3Core.xdc"
 loadConstraints -path "$::DIR_PATH/xdc/AlphaDataKu3App.xdc"
 

diff --git a/hardware/SlacPgpCardGen3/pcie/rtl/AxiPcieCrossbarIpCoreWrapper.vhd b/hardware/SlacPgpCardGen3/pcie/rtl/AxiPcieCrossbarIpCoreWrapper.vhd
@@ -16,8 +16,10 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
 
 entity AxiPcieCrossbarIpCoreWrapper is
    generic (

diff --git a/hardware/SlacPgpCardGen3/pcie/rtl/AxiPgpCardG3PciePhyWrapper.vhd b/hardware/SlacPgpCardGen3/pcie/rtl/AxiPgpCardG3PciePhyWrapper.vhd
@@ -16,10 +16,14 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiPciePkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
+use surf.AxiLitePkg.all;
+
+library axi_pcie_core;
+use axi_pcie_core.AxiPciePkg.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -185,7 +189,7 @@ begin
          O     => pciRefClk,
          ODIV2 => open);        
 
-   U_RstSync0 : entity work.RstSync
+   U_RstSync0 : entity surf.RstSync
       generic map (
          TPD_G          => TPD_G,
          IN_POLARITY_G  => '0',
@@ -204,7 +208,7 @@ begin
 
    rst <= not(rstL);
 
-   U_RstSync1 : entity work.RstSync
+   U_RstSync1 : entity surf.RstSync
       generic map (
          TPD_G          => TPD_G,
          IN_POLARITY_G  => '1',
@@ -217,7 +221,7 @@ begin
    ---------------------------------------- 
    -- Synchronize the AXI-Lite transactions
    ---------------------------------------- 
-   U_AxiLiteAsync : entity work.AxiLiteAsync
+   U_AxiLiteAsync : entity surf.AxiLiteAsync
       generic map (
          TPD_G => TPD_G)
       port map (

diff --git a/hardware/SlacPgpCardGen3/pcie/ruckus.tcl b/hardware/SlacPgpCardGen3/pcie/ruckus.tcl
@@ -1,18 +1,18 @@
 # Load RUCKUS environment and library
 source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
 
-loadSource -dir "$::DIR_PATH/rtl"
+loadSource -lib axi_pcie_core -dir "$::DIR_PATH/rtl"
 
 # loadIpCore    -path "$::DIR_PATH/ip/AxiPgpCardG3PciePhy.xci"
-loadSource      -path "$::DIR_PATH/ip/AxiPgpCardG3PciePhy.dcp"
+loadSource -lib axi_pcie_core      -path "$::DIR_PATH/ip/AxiPgpCardG3PciePhy.dcp"
 
 loadConstraints -path "$::DIR_PATH/ip/AxiPgpCardG3PciePhy.xdc"
 set_property PROCESSING_ORDER {EARLY}               [get_files {AxiPgpCardG3PciePhy.xdc}]
 set_property SCOPED_TO_REF    {AxiPgpCardG3PciePhy} [get_files {AxiPgpCardG3PciePhy.xdc}]
 set_property SCOPED_TO_CELLS  {inst}                [get_files {AxiPgpCardG3PciePhy.xdc}]
 
 # loadIpCore    -path "$::DIR_PATH/ip/AxiPcieCrossbarIpCore.xci"
-loadSource      -path "$::DIR_PATH/ip/AxiPcieCrossbarIpCore.dcp"
+loadSource -lib axi_pcie_core      -path "$::DIR_PATH/ip/AxiPcieCrossbarIpCore.dcp"
 loadConstraints -path "$::DIR_PATH/ip/AxiPcieCrossbarIpCore.xdc"
 
 set_property PROCESSING_ORDER {LATE}                  [get_files {AxiPcieCrossbarIpCore.xdc}]

diff --git a/hardware/SlacPgpCardGen3/rtl/AxiPcieCrossbar.vhd b/hardware/SlacPgpCardGen3/rtl/AxiPcieCrossbar.vhd
@@ -16,8 +16,11 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
+
+library axi_pcie_core;
 
 entity AxiPcieCrossbar is
    generic (
@@ -59,7 +62,7 @@ begin
    -------------------
    -- AXI XBAR IP Core
    -------------------
-   U_AxiXbar : entity work.AxiPcieCrossbarIpCoreWrapper
+   U_AxiXbar : entity axi_pcie_core.AxiPcieCrossbarIpCoreWrapper
       generic map(
          TPD_G             => TPD_G,
          AXI_PCIE_CONFIG_G => AXI_PCIE_CONFIG_G)

diff --git a/hardware/SlacPgpCardGen3/rtl/AxiPciePgpCardG3Core.vhd b/hardware/SlacPgpCardGen3/rtl/AxiPciePgpCardG3Core.vhd
@@ -19,11 +19,15 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiStreamPkg.all;
-use work.AxiPciePkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
+use surf.AxiLitePkg.all;
+use surf.AxiStreamPkg.all;
+
+library axi_pcie_core;
+use axi_pcie_core.AxiPciePkg.all;
 
 library unisim;
 use unisim.vcomponents.all;
@@ -115,7 +119,7 @@ begin
 
    dmaClk <= sysClock;
 
-   U_Rst : entity work.RstPipeline
+   U_Rst : entity surf.RstPipeline
       generic map (
          TPD_G => TPD_G)
       port map (
@@ -129,7 +133,7 @@ begin
    -- AXI PCIe PHY
    ---------------   
    REAL_PCIE : if (not ROGUE_SIM_EN_G) generate
-      U_AxiPciePhy : entity work.AxiPgpCardG3PciePhyWrapper
+      U_AxiPciePhy : entity axi_pcie_core.AxiPgpCardG3PciePhyWrapper
          generic map (
             TPD_G => TPD_G)
          port map (
@@ -160,7 +164,7 @@ begin
             pciTxN         => pciTxN);
    end generate;
    SIM_PCIE : if (ROGUE_SIM_EN_G) generate
-      U_sysClock : entity work.ClkRst
+      U_sysClock : entity surf.ClkRst
          generic map (
             CLK_PERIOD_G      => 4 ns,  -- 250 MHz
             RST_START_DELAY_G => 0 ns,
@@ -173,7 +177,7 @@ begin
    ---------------
    -- AXI PCIe REG
    --------------- 
-   U_REG : entity work.AxiPcieReg
+   U_REG : entity axi_pcie_core.AxiPcieReg
       generic map (
          TPD_G                => TPD_G,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
@@ -237,7 +241,7 @@ begin
    ---------------
    -- AXI PCIe DMA
    ---------------   
-   U_AxiPcieDma : entity work.AxiPcieDma
+   U_AxiPcieDma : entity axi_pcie_core.AxiPcieDma
       generic map (
          TPD_G                => TPD_G,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,

diff --git a/hardware/SlacPgpCardGen3/rtl/AxiPciePkg.vhd b/hardware/SlacPgpCardGen3/rtl/AxiPciePkg.vhd
@@ -16,10 +16,12 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiLitePkg.all;
-use work.AxiStreamPkg.all;
-use work.AxiPkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+use surf.AxiStreamPkg.all;
+use surf.AxiPkg.all;
 
 package AxiPciePkg is
 

diff --git a/hardware/SlacPgpCardGen3/ruckus.tcl b/hardware/SlacPgpCardGen3/ruckus.tcl
@@ -16,12 +16,12 @@ if { [VersionCheck 2018.2] < 0 } {exit -1}
 # 7-Series PCIe IP core appear to not support 40-bit address (even with 64-bit enabled)
 #######################################################################################
 # loadRuckusTcl "$::DIR_PATH/../../shared"
-loadSource -path "$::DIR_PATH/../../shared/rtl/AxiPcieDma.vhd"
-loadSource -path "$::DIR_PATH/../../shared/rtl/AxiPcieReg.vhd"
-loadSource -path "$::DIR_PATH/../../shared/rtl/AxiPcieRegWriteDeMux.vhd"
+loadSource -lib axi_pcie_core -path "$::DIR_PATH/../../shared/rtl/AxiPcieDma.vhd"
+loadSource -lib axi_pcie_core -path "$::DIR_PATH/../../shared/rtl/AxiPcieReg.vhd"
+loadSource -lib axi_pcie_core -path "$::DIR_PATH/../../shared/rtl/AxiPcieRegWriteDeMux.vhd"
 
 # Load local Source Code and Constraints
-loadSource      -dir "$::DIR_PATH/rtl"
+loadSource -lib axi_pcie_core      -dir "$::DIR_PATH/rtl"
 loadConstraints -dir "$::DIR_PATH/xdc"
 
 # Load the primary PCIe core

diff --git a/hardware/XilinxAc701/pcie/rtl/AxiPcieCrossbarIpCoreWrapper.vhd b/hardware/XilinxAc701/pcie/rtl/AxiPcieCrossbarIpCoreWrapper.vhd
@@ -16,8 +16,10 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-use work.StdRtlPkg.all;
-use work.AxiPkg.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiPkg.all;
 
 entity AxiPcieCrossbarIpCoreWrapper is
    generic (