Merge pull request #100 from slaclab/pre-release

Release Candidate v3.12.0
slaclab · May 12, 2023 · b00fb3b · b00fb3b
2 parents 8c53ec9 + 3ab27a3
commit b00fb3b
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Showing 12 changed files with 1,045 additions and 16 deletions.
diff --git a/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-3x16/rtl/XilinxAlveoU55cCore.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxAlveoU55cCore is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports

diff --git a/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd b/hardware/XilinxAlveoU55c/pcie-4x8/rtl/XilinxAlveoU55cCore.vhd
@@ -34,7 +34,7 @@ use unisim.vcomponents.all;
 entity XilinxAlveoU55cCore is
    generic (
       TPD_G                : time                        := 1 ns;
-      SI5394_INIT_FILE_G   : string                      := "none";
+      SI5394_INIT_FILE_G   : string                      := "Si5394A_GT_REFCLK_156MHz.mem";
       ROGUE_SIM_EN_G       : boolean                     := false;
       ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
       ROGUE_SIM_CH_COUNT_G : natural range 1 to 256      := 256;
@@ -215,7 +215,7 @@ begin
             TPD_G              => TPD_G,
             MEMORY_INIT_FILE_G => SI5394_INIT_FILE_G,
             I2C_BASE_ADDR_G    => "00",
-            I2C_SCL_FREQ_G     => 400.0E+3,        -- units of Hz
+            I2C_SCL_FREQ_G     => 100.0E+3,        -- units of Hz
             AXIL_CLK_FREQ_G    => DMA_CLK_FREQ_C)  -- units of Hz
          port map (
             -- I2C Ports