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Merge pull request #53 from slaclab/pre-release
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v3.1.1 release candidate
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@ruck314
ruck314 authored Jan 23, 2020
2 parents f98004f + 271eb9b commit d350861
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Showing 9 changed files with 447 additions and 365 deletions.
6 changes: 3 additions & 3 deletions hardware/SlacPgpCardG4/xdc/SlacPgpCardGen4App.xdc
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Expand Up @@ -66,9 +66,9 @@ set_property PACKAGE_PIN H6 [get_ports { sfpRefClkP[1] }] ;# 371.428571 MHz
set_property PACKAGE_PIN H5 [get_ports { sfpRefClkN[1] }] ;# 371.428571 MHz

set_property PACKAGE_PIN F6 [get_ports { sfpTxP }]
set_property PACKAGE_PIN F5 [get_ports { sfpRxP }]
set_property PACKAGE_PIN E4 [get_ports { sfpRxN }]
set_property PACKAGE_PIN E3 [get_ports { sfpTxN }]
set_property PACKAGE_PIN F5 [get_ports { sfpTxN }]
set_property PACKAGE_PIN E4 [get_ports { sfpRxP }]
set_property PACKAGE_PIN E3 [get_ports { sfpRxN }]

#############
# QSFP[1:0] #
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2 changes: 1 addition & 1 deletion protocol/gpuAsync/rtl/AxiPcieGpuAsyncCore.vhd
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Expand Up @@ -67,7 +67,7 @@ architecture mapping of AxiPcieGpuAsyncCore is
TDATA_BYTES_C => AXI_PCIE_CONFIG_C.DATA_BYTES_C, -- Match the AXI and AXIS widths for M_AXI port
TDEST_BITS_C => 8,
TID_BITS_C => 8,
TKEEP_MODE_C => TKEEP_COMP_C,
TKEEP_MODE_C => TKEEP_COUNT_C, -- AXI DMA V2 uses TKEEP_COUNT_C to help meet timing
TUSER_BITS_C => 8,
TUSER_MODE_C => TUSER_FIRST_LAST_C);

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195 changes: 3 additions & 192 deletions python/axipcie/_AxiPcieCore.py
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Expand Up @@ -14,200 +14,11 @@
import surf.devices.micron as micron
import surf.xilinx as xil

class PcieAxiVersion(axi.AxiVersion):
def __init__(self,
name = 'AxiVersion',
description = 'AXI-Lite Version Module',
numUserConstants = 0,
**kwargs):
super().__init__(
name = name,
description = description,
**kwargs
)

self.add(pr.RemoteVariable(
name = 'DMA_SIZE_G',
offset = 0x400+(4*0),
bitSize = 32,
mode = 'RO',
))

self.add(pr.RemoteVariable(
name = 'Reserved',
offset = 0x400+(4*1),
bitSize = 32,
mode = 'RO',
))

self.add(pr.RemoteVariable(
name = 'DRIVER_TYPE_ID_G',
offset = 0x400+(4*2),
bitSize = 32,
mode = 'RO',
))

self.add(pr.RemoteVariable(
name = 'XIL_DEVICE_G',
offset = 0x400+(4*3),
bitSize = 32,
mode = 'RO',
enum = {
0x0: 'ULTRASCALE',
0x1: '7SERIES',
},
))

self.add(pr.RemoteVariable(
name = 'DMA_CLK_FREQ_C',
offset = 0x400+(4*4),
bitSize = 32,
mode = 'RO',
disp = '{:d}',
units = 'Hz',
))
import axipcie

self.add(pr.RemoteVariable(
name = 'BOOT_PROM_G',
offset = 0x400+(4*5),
bitSize = 32,
mode = 'RO',
enum = {
0x0: 'BPI',
0x1: 'SPIx8',
0x2: 'SPIx4',
},
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TDATA_BYTES_C',
offset = 0x400+(4*6),
bitSize = 8,
bitOffset = 24,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TDEST_BITS_C',
offset = 0x400+(4*6),
bitSize = 4,
bitOffset = 20,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TUSER_BITS_C',
offset = 0x400+(4*6),
bitSize = 4,
bitOffset = 16,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TID_BITS_C',
offset = 0x400+(4*6),
bitSize = 4,
bitOffset = 12,
mode = 'RO',
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TKEEP_MODE_C',
offset = 0x400+(4*6),
bitSize = 4,
bitOffset = 8,
mode = 'RO',
enum = {
0x0: 'TKEEP_NORMAL_C',
0x1: 'TKEEP_COMP_C',
0x2: 'TKEEP_FIXED_C',
0x3: 'TKEEP_COUNT_C',
},
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TUSER_MODE_C',
offset = 0x400+(4*6),
bitSize = 4,
bitOffset = 4,
mode = 'RO',
enum = {
0x0: 'TUSER_NORMAL_C',
0x1: 'TUSER_FIRST_LAST_C',
0x2: 'TUSER_LAST_C',
0x3: 'TUSER_NONE_C',
},
))

self.add(pr.RemoteVariable(
name = 'DMA_AXIS_CONFIG_G_TSTRB_EN_C',
offset = 0x400+(4*6),
bitSize = 1,
bitOffset = 1,
mode = 'RO',
base = pr.Bool,
))

self.add(pr.RemoteVariable(
name = 'AppReset',
offset = 0x400+(4*6),
bitSize = 1,
bitOffset = 0,
mode = 'RO',
base = pr.Bool,
pollInterval = 1,
))

self.add(pr.RemoteVariable(
name = 'AXI_PCIE_CONFIG_C_ADDR_WIDTH_C',
offset = 0x400+(4*7),
bitSize = 8,
bitOffset = 24,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'AXI_PCIE_CONFIG_C_DATA_BYTES_C',
offset = 0x400+(4*7),
bitSize = 8,
bitOffset = 16,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'AXI_PCIE_CONFIG_C_ID_BITS_C',
offset = 0x400+(4*7),
bitSize = 8,
bitOffset = 8,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = 'AXI_PCIE_CONFIG_C_LEN_BITS_C',
offset = 0x400+(4*7),
bitSize = 8,
bitOffset = 0,
mode = 'RO',
disp = '{:d}',
))

self.add(pr.RemoteVariable(
name = "AppClkFreq",
description = "Application Clock Frequency",
offset = 0x400+(4*8),
units = 'Hz',
disp = '{:d}',
mode = "RO",
pollInterval = 1
))

class AxiPcieCore(pr.Device):
"""This class maps to axi-pcie-core/shared/rtl/AxiPcieReg.vhd"""
def __init__(self,
description = 'Base components of the PCIe firmware core',
useBpi = False,
Expand All @@ -223,7 +34,7 @@ def __init__(self,
))

# AxiVersion Module
self.add(PcieAxiVersion(
self.add(axipcie.PcieAxiVersion(
offset = 0x20000,
expand = False,
))
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27 changes: 27 additions & 0 deletions python/axipcie/_AxiPcieDma.py
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@@ -0,0 +1,27 @@
import rogue
from collections import defaultdict

def createAxiPcieMemMap(driverPath, host='localhost', port=8000):
"""Provides BAR0 access to AxiPcieCore"""
if driverPath != 'sim':
return rogue.hardware.axi.AxiMemMap(driverPath)
else:
return rogue.interfaces.memory.TcpClient(host, port)

def createAxiPcieDmaStreams(driverPath, streamMap, host='localhost', basePort=8000):
"""Provides DMA stream access for AxiPcieCore"""
d = defaultdict(dict)
for lane, dests in streamMap.items():
for dest in dests:
if driverPath != 'sim':
d[lane][dest] = rogue.hardware.axi.AxiStreamDma(driverPath, (0x100*lane)|dest, True)
else:
d[lane][dest] = rogue.interfaces.stream.TcpClient(host, (basePort+2)+(512*lane)+2*dest)
return d







15 changes: 15 additions & 0 deletions python/axipcie/_AxiPcieRoot.py
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@@ -0,0 +1,15 @@
import axipcie as pcie

import pyrogue as pr
import rogue

class AxiPcieRoot(pr.Root):
def __init__(self, dev, **kwargs):
super().__init__(**kwargs)

memMap = rogue.hardware.axi.AxiMemMap(dev)

self.add(pcie.AxiPcieCore(
memBase = memMap,
useBpi = True,
useSpi = True))
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