Pull Requests Since v5.0.1
Unlabeled
- #124 - Adding GPU ASYNC AXI-Lite interface to axi-pcie-core with fixed address offset
- #122 - Reset buffer index when read/write enable = 0, and ensure buffer index stays in range
Pull Request Details
Reset buffer index when read/write enable = 0, and ensure buffer index stays in range
| Author: | Larry Ruckman [email protected] |
| Date: | Tue Nov 5 14:51:17 2024 -0800 |
| Pull: | #122 (10 additions, 2 deletions, 1 files changed) |
| Branch: | slaclab/gpuAsync-buff-index |
Notes:
This fixes a couple of problems that popped up during testing:
- Single-threaded software could get confused if the buffer index does not start at 0 for a given "session". Currently, there is no way for software to detect the buffer index or reset it (without triggering userReset or something).
- If we run the software with 4 buffers, terminate when the buffer index > 1, then run the software with 2 buffers, the FPGA ends up in a weird state where the buffer index is out of range.
I tested this firmware on daq-tst-dev06.
Adding GPU ASYNC AXI-Lite interface to axi-pcie-core with fixed address offset
| Author: | Larry Ruckman [email protected] |
| Date: | Tue Nov 5 17:07:37 2024 -0800 |
| Pull: | #124 (254 additions, 41 deletions, 19 files changed) |
| Branch: | slaclab/add_gpu_off |
Notes:
Description
- Added the mapping of axilite XBAR to gpuAsyncCore in AxiPcieReg.vhd
GPU_INDEX_C => ( baseAddr => x"0002_8000", addrBits => 15,