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Patch Release v3.11.3
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@ruck314 ruck314 released this 03 Apr 20:35
· 105 commits to main since this release
v3.11.3
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Pull Requests Since v3.11.2

Bug

  1. #96 - Properly synchronize resets in AxiPcieReg

Pull Request Details

Properly synchronize resets in AxiPcieReg
Author: Larry Ruckman [email protected]
Date: Mon Apr 3 13:33:31 2023 -0700
Pull: #96 (39 additions, 17 deletions, 1 files changed)
Branch: slaclab/reg-reset-fix
Labels: bug

Notes:

The cardResetIn signal was not being synchronized to the correct clock.
Additionally, any reset signal created with an or gate needs to pass through a RstSync block.

Not yet tested so this is a draft PR.

Assets 2
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