feat: include pole mrid for converters

statnett · Jan 10, 2025 · 37744e3 · 37744e3
1 parent 35e1e4e
commit 37744e3
Show file tree

Hide file tree

Showing 2 changed files with 12 additions and 10 deletions.
diff --git a/src/cimsparql/data_models.py b/src/cimsparql/data_models.py
@@ -163,6 +163,7 @@ class PhaseTapChangerSchema(CoercingSchema):
 class ConvertersSchema(NamedResourceSchema):
     alias: Series[str] = pa.Field(nullable=True)
     substation_mrid: Series[str] = pa.Field()
+    pole: Series[str] = pa.Field()
     status: Series[bool] = pa.Field()
     node: Series[str] = pa.Field()
     p: Series[float] = pa.Field()

diff --git a/src/cimsparql/sparql/converters.sparql b/src/cimsparql/sparql/converters.sparql
@@ -3,7 +3,7 @@ PREFIX cim:<${cim}>
 PREFIX xsd:<${xsd}>
 PREFIX SN:<${SN}>
 PREFIX ALG:<${ALG}>
-select ?mrid ?name ?alias ?p ?q ?substation_mrid ?status ?node ?connectivity_node ?controller ?controller_factor ?pole_loss ?loss0 ?loss1 ?loss2 ?vdcn ?un ?capacity
+select ?mrid ?name ?alias ?p ?q ?substation_mrid (?pole_mrid as ?pole) ?status ?node ?connectivity_node ?controller ?controller_factor ?pole_loss ?loss0 ?loss1 ?loss2 ?vdcn ?un ?capacity
 where {
   {
     select * where {
@@ -12,17 +12,18 @@ where {
         # Extract converter data
         ?converter cim:IdentifiedObject.mRID ?mrid;
                    cim:IdentifiedObject.name ?name;
-                   ALG:VoltageSourceConverter.DCPole|ALG:DCConverter.DCPole ?pole;
+                   ALG:VoltageSourceConverter.DCPole|ALG:DCConverter.DCPole ?_pole;
+                   ALG:VoltageSourceConverter.DCPole/cim:IdentifiedObject.mRID|ALG:DCConverter.DCPole/cim:IdentifiedObject.mRID ?pole_mrid;
                    ALG:VoltageSourceConverter.bridgeNominalVoltage|ALG:DCConverter.bridgeNominalVoltage ?ur;
                    ALG:VoltageSourceConverter.ratedIAC|ALG:DCConverter.currentRating ?ir.
 
-        ?pole ALG:DCPole.DCController/cim:IdentifiedObject.mRID ?controller.
+        ?_pole ALG:DCPole.DCController/cim:IdentifiedObject.mRID ?controller.
 	{
-	  select ?pole (max(xsd:float(str(?controller_factor))) / count(*) as ?controller_factor)
+	  select ?_pole (max(xsd:float(str(?controller_factor))) / count(*) as ?controller_factor)
 	  {
-	    ?converter ALG:VoltageSourceConverter.DCPole|ALG:DCConverter.DCPole ?pole.
-            ?pole ALG:DCPole.participationFactor ?controller_factor.
-	  } group by ?pole
+	    ?converter ALG:VoltageSourceConverter.DCPole|ALG:DCConverter.DCPole ?_pole.
+            ?_pole ALG:DCPole.participationFactor ?controller_factor.
+	  } group by ?_pole
 	}
 
         optional{
@@ -45,23 +46,23 @@ where {
           ?converter ALG:VoltageSourceConverter.loss0 ?_loss0;
                      ALG:VoltageSourceConverter.loss1 ?_loss1;
 		     ALG:VoltageSourceConverter.loss2 ?_loss2.
-	  ?pole cim:ConductingEquipment.BaseVoltage/cim:BaseVoltage.nominalVoltage ?_vdcn;
+	  ?_pole cim:ConductingEquipment.BaseVoltage/cim:BaseVoltage.nominalVoltage ?_vdcn;
 	}
 	bind(coalesce(?_analysis_enabled, True) as ?analysis_enabled)
 	bind(coalesce(?_loss0, 0.0) as ?loss0)
 	bind(coalesce(?_loss1, 0.0) as ?loss1)
 	bind(coalesce(?_loss2, 0.0) as ?loss2)
 	bind(coalesce(?_vdcn, 0.0) as ?vdcn)
 	bind((xsd:float(?ir) * xsd:float(?ur) * xsd:float(coalesce(?bridges, 1))/1000) as ?capacity)
-	filter(?analysis_enabled)       
+	filter(?analysis_enabled)
       }
     }
   }
 
   # Extract active and reactive power for the converter
   ?converter cim:ACDCConverter.p ?p;
              cim:ACDCConverter.q ?q.
-  
+
   optional {?converter cim:ACDCConverter.poleLossP ?_pole_loss.}
   optional {?converter ^cim:SvStatus.ConductingEquipment/cim:SvStatus.inService ?in_service .}