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feat: include pole mrid for converters
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danhje committed Jan 10, 2025
1 parent 35e1e4e commit 57e731a
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Showing 2 changed files with 5 additions and 3 deletions.
1 change: 1 addition & 0 deletions src/cimsparql/data_models.py
Original file line number Diff line number Diff line change
Expand Up @@ -163,6 +163,7 @@ class PhaseTapChangerSchema(CoercingSchema):
class ConvertersSchema(NamedResourceSchema):
alias: Series[str] = pa.Field(nullable=True)
substation_mrid: Series[str] = pa.Field()
pole: Series[str] = pa.Field()
status: Series[bool] = pa.Field()
node: Series[str] = pa.Field()
p: Series[float] = pa.Field()
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7 changes: 4 additions & 3 deletions src/cimsparql/sparql/converters.sparql
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ PREFIX cim:<${cim}>
PREFIX xsd:<${xsd}>
PREFIX SN:<${SN}>
PREFIX ALG:<${ALG}>
select ?mrid ?name ?alias ?p ?q ?substation_mrid ?status ?node ?connectivity_node ?controller ?controller_factor ?pole_loss ?loss0 ?loss1 ?loss2 ?vdcn ?un ?capacity
select ?mrid ?name ?alias ?p ?q ?substation_mrid ?pole ?status ?node ?connectivity_node ?controller ?controller_factor ?pole_loss ?loss0 ?loss1 ?loss2 ?vdcn ?un ?capacity
where {
{
select * where {
Expand All @@ -13,6 +13,7 @@ where {
?converter cim:IdentifiedObject.mRID ?mrid;
cim:IdentifiedObject.name ?name;
ALG:VoltageSourceConverter.DCPole|ALG:DCConverter.DCPole ?pole;
ALG:VoltageSourceConverter.DCPole/cim:IdentifiedObject.mRID|ALG:DCConverter.DCPole/cim:IdentifiedObject.mRID ?pole;
ALG:VoltageSourceConverter.bridgeNominalVoltage|ALG:DCConverter.bridgeNominalVoltage ?ur;
ALG:VoltageSourceConverter.ratedIAC|ALG:DCConverter.currentRating ?ir.

Expand Down Expand Up @@ -53,15 +54,15 @@ where {
bind(coalesce(?_loss2, 0.0) as ?loss2)
bind(coalesce(?_vdcn, 0.0) as ?vdcn)
bind((xsd:float(?ir) * xsd:float(?ur) * xsd:float(coalesce(?bridges, 1))/1000) as ?capacity)
filter(?analysis_enabled)
filter(?analysis_enabled)
}
}
}

# Extract active and reactive power for the converter
?converter cim:ACDCConverter.p ?p;
cim:ACDCConverter.q ?q.

optional {?converter cim:ACDCConverter.poleLossP ?_pole_loss.}
optional {?converter ^cim:SvStatus.ConductingEquipment/cim:SvStatus.inService ?in_service .}

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