Merge pull request #133 from stnolting/dependabot/submodules/neorv32-…

…fc0034f [Dependabot]: Bump neorv32 from `3d986cb` to `fc0034f`
stnolting · Dec 23, 2024 · 54235c3 · 54235c3
2 parents dc863cb + c5f812d
commit 54235c3
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Showing 2 changed files with 7 additions and 7 deletions.
diff --git a/neorv32 b/neorv32
diff --git a/src/neorv32_verilog_wrapper.vhd b/src/neorv32_verilog_wrapper.vhd
@@ -35,7 +35,6 @@ begin
   generic map ( -- [note] add configuration options as required
     -- Processor Clocking --
     CLOCK_FREQUENCY     => 100_000_000, -- clock frequency of clk_i in Hz
-    CLOCK_GATING_EN     => true,        -- enable clock gating when in sleep mode
     -- Boot Configuration --
     BOOT_MODE_SELECT    => 0,           -- boot via internal bootloader
     -- On-Chip Debugger (OCD) --
@@ -59,12 +58,12 @@ begin
     RISCV_ISA_Zknd      => true,        -- implement cryptography NIST AES decryption extension
     RISCV_ISA_Zkne      => true,        -- implement cryptography NIST AES encryption extension
     RISCV_ISA_Zknh      => true,        -- implement cryptography NIST hash extension
-    RISCV_ISA_Zksed     => true,        -- implement ShangMi block cypher extension
+    RISCV_ISA_Zksed     => true,        -- implement ShangMi block cipher extension
     RISCV_ISA_Zksh      => true,        -- implement ShangMi hash extension
     RISCV_ISA_Zxcfu     => true,        -- implement custom (instr.) functions unit
     -- Tuning Options --
-    FAST_MUL_EN         => true,        -- use DSPs for M extension's multiplier
-    FAST_SHIFT_EN       => true,        -- use barrel shifter for shift operations
+    CPU_FAST_MUL_EN     => true,        -- use DSPs for M extension's multiplier
+    CPU_FAST_SHIFT_EN   => true,        -- use barrel shifter for shift operations
     -- Physical Memory Protection (PMP) --
     PMP_NUM_REGIONS     => 4,           -- number of regions (0..16)
     PMP_MIN_GRANULARITY => 4,           -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes
@@ -90,10 +89,11 @@ begin
     -- Processor peripherals --
     IO_MTIME_EN         => true,        -- implement machine system timer (MTIME)?
     IO_UART0_EN         => true,        -- implement primary universal asynchronous receiver/transmitter (UART0)?
-    IO_UART0_RX_FIFO    => 64,          -- RX fifo depth, has to be a power of two, min 1
-    IO_UART0_TX_FIFO    => 64,          -- TX fifo depth, has to be a power of two, min 1
+    IO_UART0_RX_FIFO    => 64,          -- RX FIFO depth, has to be a power of two, min 1
+    IO_UART0_TX_FIFO    => 64,          -- TX FIFO depth, has to be a power of two, min 1
     IO_SPI_EN           => true,        -- implement serial peripheral interface (SPI)?
     IO_TWI_EN           => true,        -- implement two-wire interface (TWI)?
+    IO_TWD_EN           => true,        -- implement two-wire device (TWD)?
     IO_PWM_NUM_CH       => 2,           -- number of PWM channels to implement (0..16)
     IO_WDT_EN           => true,        -- implement watch dog timer (WDT)?
     IO_NEOLED_EN        => true,        -- implement NeoPixel-compatible smart LED interface (NEOLED)?
+4 −0		CHANGELOG.md
+93 −51		docs/datasheet/cpu.adoc
+5 −4		docs/datasheet/cpu_csr.adoc
+1 −6		docs/datasheet/overview.adoc
+10 −24		docs/datasheet/soc.adoc
+1 −1		docs/datasheet/soc_sysinfo.adoc
+0 −2		docs/userguide/content.adoc
+22 −26		docs/userguide/eclipse_ide.adoc
+74 −81		docs/userguide/simulating_the_processor.adoc
+0 −12		docs/userguide/vhdl_development_environment.adoc
+40 −37		rtl/core/neorv32_application_image.vhd
+5 −5		rtl/core/neorv32_bootloader_image.vhd
+126 −28		rtl/core/neorv32_bus.vhd
+2 −2		rtl/core/neorv32_cache.vhd
+98 −78		rtl/core/neorv32_cpu.vhd
+203 −245		rtl/core/neorv32_cpu_control.vhd
+4 −2		rtl/core/neorv32_cpu_cp_crypto.vhd
+4 −8		rtl/core/neorv32_cpu_lsu.vhd
+136 −151		rtl/core/neorv32_cpu_pmp.vhd
+25 −5		rtl/core/neorv32_package.vhd
+1 −2		rtl/core/neorv32_sysinfo.vhd
+13 −32		rtl/core/neorv32_top.vhd
+19 −19		rtl/core/neorv32_xirq.vhd
+1 −0		rtl/file_list_cpu.f
+3 −3		rtl/system_integration/neorv32_vivado_ip.tcl
+7 −7		rtl/system_integration/neorv32_vivado_ip.vhd
+0 −46		sim/ghdl.run.sh
+39 −4		sim/ghdl.sh
+51 −50		sim/neorv32_tb.vhd
+9 −8		sw/common/common.mk
+60 −54		sw/image_gen/image_gen.c
+2 −1		sw/lib/include/neorv32_cpu_csr.h
+1 −1		sw/lib/include/neorv32_sysinfo.h
+1 −1		sw/lib/source/neorv32_rte.c
+2 −2		sw/lib/source/neorv32_uart.c
+0 −1		sw/svd/neorv32.svd