Synthesizable Single-Cycle/Pipelined RISCV-RV32I (tested on DE2)

Usage

The repo was being organized, so it might be broken. Feel free to open an issue.
I'm too lazy to write this README, would be revisit this when I'm free.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
quartus		quartus
report		report
sof		sof
src		src
tb		tb
utils		utils
.gitignore		.gitignore
README.md		README.md