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[MachineLICM] Don't allow hoisting invariant loads across mem barrier… #9798

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/MachineLICM.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1474,7 +1474,7 @@ void MachineLICMBase::InitializeLoadsHoistableLoops() {
if (!AllowedToHoistLoads[Loop])
continue;
for (auto &MI : *MBB) {
if (!MI.mayStore() && !MI.isCall() &&
if (!MI.isLoadFoldBarrier() && !MI.mayStore() && !MI.isCall() &&
!(MI.mayLoad() && MI.hasOrderedMemoryRef()))
continue;
for (MachineLoop *L = Loop; L != nullptr; L = L->getParentLoop())
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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
Original file line number Diff line number Diff line change
Expand Up @@ -497,6 +497,35 @@ for.exit: ; preds = %for.body
ret i64 %spec.select
}

@a = external local_unnamed_addr global i32, align 4

; Make sure the load is not hoisted out of the loop across memory barriers.
define i32 @load_between_memory_barriers() {
; CHECK-LABEL: load_between_memory_barriers:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, :got:a
; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
; CHECK-NEXT: .LBB8_1: // %loop
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: //MEMBARRIER
; CHECK-NEXT: ldr w0, [x8]
; CHECK-NEXT: //MEMBARRIER
; CHECK-NEXT: cbz w0, .LBB8_1
; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret
br label %loop

loop:
fence syncscope("singlethread") acq_rel
%l = load i32, ptr @a, align 4
fence syncscope("singlethread") acq_rel
%c = icmp eq i32 %l, 0
br i1 %c, label %loop, label %exit

exit:
ret i32 %l
}

declare i32 @bcmp(ptr, ptr, i64)
declare i32 @memcmp(ptr, ptr, i64)
declare void @func()
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Mips/lcb5.ll
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ if.end: ; preds = %if.then, %entry
}

; ci: .ent z3
; ci: bteqz $BB6_3
; ci: bteqz $BB6_2
; ci: .end z3

; Function Attrs: nounwind optsize
Expand All @@ -210,7 +210,7 @@ if.end: ; preds = %if.then, %entry

; ci: .ent z4
; ci: btnez $BB7_1 # 16 bit inst
; ci: jal $BB7_3 # branch
; ci: jal $BB7_2 # branch
; ci: nop
; ci: $BB7_1:
; ci: .p2align 2
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