coreboot: Fix RTC being reset on boot

Cherry-pick the following upstream commits: - coreboot/coreboot@fb401e74da0c: soc/intel/alderlake: Sync UPD Usb4CmMode with Kconfig - coreboot/coreboot@961ed9fe2710: soc/intel/adl: Set slp-s0 counter frequency - coreboot/coreboot@377845a9d4f3: soc/intel/tigerlake: Fix processor hang while plug unplug of TBT device - coreboot/coreboot@354a54ac84a9: soc/intel/tigerlake: Remove IOM Mctp command from TCSS ASL - coreboot/coreboot@adf042f6c61e: lib/rtc: Fix off-by-one error in February day count in leap year This also brings in the WIP addw4, but that will documented in the PR that adds full support for the board. Signed-off-by: Tim Crawford <[email protected]>
system76 · Mar 1, 2024 · 120c2fd · 120c2fd
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commit 120c2fd
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diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -21,6 +21,10 @@ features apply to your model and firmware version, see the
 - adl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
 - rpl: Fixed PCIe 4.0 drives in PCIe 3.0 slot failing to initialize on resume
 - rpl: Fixed TCSS ACPI access
+- adl: Fixed `SLP_S0#` counter frequency
+- rpl: Fixed `SLP_S0#` counter frequency
+- tgl: Fixed TBT ACPI
+- Fixed RTC being reset on boot during February 29th
 
 ## 2024-01-18
 

diff --git a/coreboot b/coreboot
+1 −1		src/lib/rtc.c
+14 −3		src/mainboard/system76/rpl/Kconfig
+3 −0		src/mainboard/system76/rpl/Kconfig.name
+1 −1		src/mainboard/system76/rpl/devicetree.cb
+12 −0		src/mainboard/system76/rpl/variants/addw4/board.fmd
+2 −0		src/mainboard/system76/rpl/variants/addw4/board_info.txt
+ −		src/mainboard/system76/rpl/variants/addw4/data.vbt
+294 −0		src/mainboard/system76/rpl/variants/addw4/gpio.c
+16 −0		src/mainboard/system76/rpl/variants/addw4/gpio_early.c
+52 −0		src/mainboard/system76/rpl/variants/addw4/hda_verb.c
+12 −0		src/mainboard/system76/rpl/variants/addw4/include/variant/gpio.h
+101 −0		src/mainboard/system76/rpl/variants/addw4/overridetree.cb
+43 −0		src/mainboard/system76/rpl/variants/addw4/romstage.c
+5 −0		src/soc/intel/alderlake/Kconfig
+4 −0		src/soc/intel/alderlake/fsp_params.c
+9 −142		src/soc/intel/tigerlake/acpi/tcss.asl
+2 −1		src/soc/intel/tigerlake/acpi/tcss_dma.asl