merging dev-loongarch to lastest dev

.gitignore

@@ -25,4 +25,5 @@ Image*
 *.qcow2
 *.dtb
 .DS_Store
-flash.img*
+flash.img*
+.DS_Store

.vscode/settings.json

@@ -72,11 +72,11 @@
 	// "rust.target": "loongarch64-unknown-none",
 	"rust.all_targets": false,
 	// For Rust Analyzer plugin users:
-	"rust-analyzer.cargo.target": "aarch64-unknown-none",
+	// "rust-analyzer.cargo.target": "aarch64-unknown-none",
 	// "rust-analyzer.cargo.target": "riscv64gc-unknown-none-elf",
-	// "rust-analyzer.cargo.target": "loongarch64-unknown-none",
+	"rust-analyzer.cargo.target": "loongarch64-unknown-none",
 	"rust-analyzer.checkOnSave.allTargets": false,
 	"rust-analyzer.cargo.features": [
-	    "platform_qemu"
+	    // "platform_qemu"
 	]
 }

Cargo.toml

@@ -16,11 +16,11 @@ tock-registers = "0.8"
 lazy_static = { version = "1.4", features = ["spin_no_std"] }
 bitmap-allocator = { git = "https://github.com/rcore-os/bitmap-allocator", rev = "03bd9909" }
 fdt = { path = "./vendor/fdt" }
+qemu-exit = "3.0.2"
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
 aarch64-cpu = "9.4.0"
 psci = { version = "0.1.0", default-features = false, features = ["smc"]}
-qemu-exit = "3.0.2"
 
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 sbi-rt = { version = "0.0.2", features = ["legacy"] }

Makefile

@@ -52,7 +52,8 @@ elf:
 
 disa:
 	readelf -a $(hvisor_elf) > hvisor-elf.txt
-	rust-objdump --disassemble $(hvisor_elf) > hvisor.S
+# rust-objdump --disassemble $(hvisor_elf) > hvisor.S
+	rust-objdump --disassemble --source $(hvisor_elf) > hvisor.S
 
 run: all
 	$(QEMU) $(QEMU_ARGS)

rust-toolchain.toml

@@ -1,5 +1,5 @@
 [toolchain]
 profile = "minimal"
 # use the nightly version of the last stable toolchain, see <https://forge.rust-lang.org/>
-channel = "nightly-2024-10-01"
+channel = "nightly-2023-12-28"
 components = ["rust-src", "llvm-tools-preview", "rustfmt", "clippy"]

scripts/3a5000-loongarch64.mk

@@ -11,13 +11,12 @@ HVISOR_ENTRY_PA := 0x9000000080000000
 # so no qemu related stuff here, we have to debug it on 
 # REAL hardware with UEFI firmware interface
 
-# QEMU := qemu-system-loongarch64
-# QEMU_ARGS := -machine virt
-# QEMU_ARGS += -bios default
-# QEMU_ARGS += -smp 4
-# QEMU_ARGS += -m 2G
-# QEMU_ARGS += -nographic
-# QEMU_ARGS += -kernel $(hvisor_bin)
+QEMU := qemu-system-loongarch64
+QEMU_ARGS := -machine virt
+QEMU_ARGS += -smp 4
+QEMU_ARGS += -m 2G
+QEMU_ARGS += -nographic
+QEMU_ARGS += -kernel $(hvisor_elf)
 # QEMU_ARGS += -device loader,file="$(zone0_kernel)",addr=0x90000000,force-raw=on
 # QEMU_ARGS += -device loader,file="$(zone0_dtb)",addr=0x8f000000,force-raw=on
 

src/arch/loongarch64/cpu.rs

@@ -1,10 +1,12 @@
 use super::ipi::*;
 use super::zone::ZoneContext;
+use crate::arch::zone::disable_hwi_through;
 use crate::device::common::MMIODerefWrapper;
 use crate::percpu::this_cpu_data;
 use core::arch::asm;
 use core::fmt::{self, Debug, Formatter};
-use loongArch64::register::cpuid;
+use loongArch64::register::{cpuid, crmd};
+use loongArch64::register::crmd::Crmd;
 use loongArch64::register::pgdl;
 use tock_registers::interfaces::Writeable;
 
@@ -49,13 +51,13 @@ impl ArchCpu {
         this_cpu_data().activate_gpm();
         self.power_on = true;
         if !self.init {
-            self.init(
-                this_cpu_data().cpu_on_entry,
-                this_cpu_data().id,
-                0,
-            );
+            self.init(this_cpu_data().cpu_on_entry, this_cpu_data().id, 0);
             self.init = true;
         }
+        // set x[] to all 0
+        for i in 0..32 {
+            self.ctx.x[i] = 0;
+        }
         info!(
             "loongarch64: CPU{} run@{:#x}",
             self.get_cpuid(),
@@ -80,6 +82,14 @@ impl ArchCpu {
             self.stack_top()
         );
 
+        let cpuid = self.get_cpuid();
+        if cpuid != 0 {
+            // on loongarch64 we only allow direct interrupt through on cpu0 with rootlinux
+            // root linux use cpuintc->liointc->uart0 for IO irqs, we put it through to use uart0
+            // on nonroot, we only need to inject virtio irq so let's disable it - wheatfox
+            disable_hwi_through();
+        }
+
         unsafe {
             asm!(
                 "csrwr {}, {LOONGARCH_CSR_SAVE3}",
@@ -91,12 +101,29 @@ impl ArchCpu {
             );
         }
 
+        unsafe {
+            asm!("invtlb 0, $r0, $r0"); // flush TLBs
+        }
+
         super::trap::_vcpu_return(ctx_addr as usize);
 
         panic!("loongarch64: ArchCpu::run: unreachable");
     }
-    pub fn idle(&self) -> ! {
+    pub fn idle(&mut self) -> ! {
+        let ctx_addr = &mut self.ctx as *mut ZoneContext;
+        unsafe {
+            asm!(
+                "csrwr {}, {LOONGARCH_CSR_SAVE3}",
+                "csrwr {}, {LOONGARCH_CSR_SAVE4}",
+                in(reg) (ctx_addr as usize + core::mem::size_of::<ZoneContext>()),
+                in(reg) self.stack_top(),
+                LOONGARCH_CSR_SAVE3 = const 0x33,
+                LOONGARCH_CSR_SAVE4 = const 0x34,
+            );
+        }
         info!("loongarch64: ArchCpu::idle: cpuid={}", self.get_cpuid());
+        // enable ipi on ecfg
+        ecfg_ipi_enable();
         loop {}
     }
 }