Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

risc-v/mpfs: clear L2 before use #145

Merged
merged 1 commit into from
Aug 15, 2023
Merged

risc-v/mpfs: clear L2 before use #145

merged 1 commit into from
Aug 15, 2023

Commits on Aug 15, 2023

  1. risc-v/mpfs: clear L2 before use 

    SiFive document: "ECC Error Handling Guide" states:

"Any SRAM block or cache memory containing ECC functionality needs to be
initialized prior to use. ECC will correct defective bits based on memory
contents, so if memory is not first initialized to a known state, then ECC
will not operate as expected. It is recommended to use a DMA, if available,
to write the entire SRAM or cache to zeros prior to enabling ECC reporting.
If no DMA is present, use store instructions issued from the processor."

Clean the cache at this early stage so no ECC errors will be flooding later.

Signed-off-by: Eero Nurkkala <[email protected]>
    @eenurkka
    eenurkka committed Aug 15, 2023
    Configuration menu
    Copy the full SHA
    4517fcf View commit details
    Browse the repository at this point in the history