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Jetson start #209
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Jetson start #209
Commits on Aug 25, 2023
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boards/riscv/mpfs/icicle/configs/standalone: Add a standalone target
- boots from eNVM - uses lim memory for RAM - has console on uart 0 - has procfs enabled - has most of nsh commands enabled Signed-off-by: Jukka Laitinen <[email protected]>
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Fix the check workflow for tiiuae repo
- Change git repository urls to point to our tiiuae repos for nuttx & nuttx apps - Remove most of the the build steps, leave just arm-12 and riscv; arm-12 has a build for stm32f7, and riscv for mpfs Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/opensbi/Make.defs: Switch opensbi to the nuttx/size o…
…ptimized version in tiiuae repo Signed-off-by: Jukka Laitinen <[email protected]>
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[REVERTME] arch/risc-v/src/mpfs/mpfs_ethernet.c: Hack the ethernet dr…
…iver to re-initialize on rx timeout If the interface is UP, and no packets are received in 30s, re-initialize the interface by calling the already implemented mpfs_txtimeout_expiry. This is a temporary workaround for a bug where IF might be UP and working but packets can only be transmitted. Receive side just doesn't work at all. The original bug can be re-produced easily by disconnecting and reconnecting the ethernet cable while the IF is up. Signed-off-by: Jukka Laitinen <[email protected]>
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[HACK] Set SD-card speed to 50MHz
SD-card clock speed is just forced to 50MHz. Note that to be correct, one should first set the SD-card into high-speed mode, but currently NuttX doesn't support this. With our cards, just setting the interface to 50MHz seems to work fine, and it removes the issue with 25MHZ clock causing disturbance on GPS bands. Typically cards which support high-speed mode just work with 50MHz interface clock. This patch should be reverted when the NuttX supports high-speed mode, and we can properly set it. Signed-off-by: Jukka Laitinen <[email protected]>
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Fix standalone defconfig for CI
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_clockconfig.c: Flag out code only used in b…
…ootloader This removes the need to have all the DDR/clock configuration related "LIBERODEFS" flags defined, when not building a standalone/coldboot configuration All of this code is unused when not building with CONFIG_MPFS_BOOTLOADER Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs/emmcsd: [HACK] Set 8-bit data width and DDR HS mode for eMMC
This is not the correct way to do this, but it gives a nice perf. boost
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drivers/net/rpmsgdrv.c: Support only TRANSFER commands
All other commands are disabled in send_recv(). Signed-off-by: Jani Paalijarvi <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ihc.c: Increase RPMSG buffer size
Signed-off-by: Jani Paalijarvi <[email protected]>
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arch/risc-v/src/mpfs/mpfs_fpga_canfd.c: Fix CONFIG_DEBUG_CAN_INFO ifd…
…ef and forward declare devif_loopback Signed-off-by: Jukka Laitinen <[email protected]>
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boards/risc-v/mpfs/icicle/configs/canfd/defconfig: Normalize
Signed-off-by: Jukka Laitinen <[email protected]>
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remove devif_loopback in canfd driver since it is now devif_poll func…
… that takes care of the need for loopback
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arch/risc-v/src/mpfs/mpfs_ihc.c: Minor fixes
Remove unnecessary VQID shifting (16 -> 0). Give an error if RPTUN init fails.
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Remove MPFS_IHC_LINUX_ON_HART4 from default configurations
Enable LINUX_ON_HART4 in rpmsg-ch2 defconfig of ICICLE board. Remove LINUX_ON_HART4 config from rpmsg-ch1 defconfig of ICICLE board.
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arch/arm/src/stm32f7/stm32_ethernet.c: Fix "unused variable" warning
Fix build warning when CONFIG_STM32F7_AUTONEG is not set Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_userspace.c: Map MTIME into userspace reser…
…ved IO area in protected build Signed-off-by: Jukka Laitinen <[email protected]>
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boards/risc-v/mpfs/icicle: Add USRIO area for userspace IO mappings
Signed-off-by: Jukka Laitinen <[email protected]>
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Add mpfs crypto driver into nuttx build
Signed-off-by: Jukka Laitinen <[email protected]>
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mpfs/mpfs_mm_init: Add the MTIME user mapping for kernel mode as well
Just a temporary patch, need to implement some kind of scalable solution for this. It might be a good idea to map something else for the user to avoid using ecall to enter the kernel for simple reads ? Also, increase the L3 table size
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arch/risc-v/src/mpfs/Kconfig: Don't source crypto/Kconfig
There is no make step executed for this directory before the Kconfigure, so all Kconfig's just need to be in-tree Signed-off-by: Jukka Laitinen <[email protected]>
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arch/riscv/src/mpfs/mpfs_ethernet.c: discard err rxframe in int work
Workaround to avoid deadlock situation: The RX shall not try to wait for complete frame in case there is RX errors detected. In case mpfs_receive is called, it keeps waiting for complete frame and also keeps the net_lock locked. In the mean while, the TX may run out of free descriptors, but can not get net_lock mutex lock to be able to release used descriptors. If there are no free TX descs it disables RX interrupts because it may require to send response to the received frame. So, TX side keeps RX interrupts disabled due to lack of free descriptors and RX blocks TX to release those descs by stubbornly waiting for complete frame.
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arch/risc-v/src/mpfs/crypto.defs: Update to include mpfs_systemservice.c
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Generate an unique locally administrated MAC ad…
…dress Add a function to read PolarFire's serial number from system controller, and use the first five digits as device's mac address Signed-off-by: Jukka Laitinen <[email protected]>
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emmc interrupt blackout issue fix
sendfifo() function need enable BWR_IE before checking if BWE is enabled to avoid BWE to be activated between the BWE check and BWR interrupt enabling, which causes the interrupt to be missed and Data Timeout error.
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mpfs/mpfs_userspace: Increase user space size to 8MB
The user i/o area goes over 4MB, so need more page tables
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test: bootloader: apply ihc flow control
If Linux kernel sends data, block all incoming msgs from the remote end until an ack arrives, which completes the linux send data command. If other than ack arrives, the logic in the Linux is no longer maintained, causing the virtio marked broken. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: apply ihc software flow control
Utilize the sw flow control. Also detect situations where both ack and msg present is set. In that case, consider both flags. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: ihc: use work queue instead of thread
The thread conflicts with a HPWORK originated network operation, taking the net_lock() recursive mutex, resulting in a deadlock. Recursive mutexes are OK within the same task (HPWORK), so apply the thread work into a work instead, which would potentially resolve the very random conflict. This increases the data throughput also a bit (10 - 20%). Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: serial: add fpga uarts
Add FPGA serial support, including console capabilities. FPGA has UARTs from 0-7, so all UARTs starting from 5 depend on FPGA. Signed-off-by: Eero Nurkkala <[email protected]>
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Add CONFIG_MPFS_SPI flag to define using SOC hard-ip SPI block
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Remove CONFIG_MPFS_COREPWMx_PWMCLK configs
These are always the same as FPGA peripheral clock, so use that directly Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: serial: fix uart closing
Don't turn off FIC3 clk which would terminate all other peripherals depending on it. Also add a few missing undefs. Signed-off-by: Eero Nurkkala <[email protected]>
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Change MPFS_FPGA_UARTx_BASE addresses to 4k aligned as per new FPGA i…
…mage Signed-off-by: Jukka Laitinen <[email protected]>
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[REVERTME] arch/risc-v/src/mpfs/mpfs_corespi.c: Hack around a bug in …
…nuttx nxsem_tickwait_uninterruptible bug The nxsem_tickwait_uninterruptible seems to timeout randomly one tick too soon. Add one tick to timeout to make sure it is long enough. This can be reverted when the actual bug is fixed. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_timerisr.c: Partially revert common mtime d…
…river change Revert: commit 1975878 Author: Huang Qi <[email protected]> Date: Mon Apr 11 18:42:24 2022 +0800 arch/risc-v: Apply common mtime driver to mtime based chps Signed-off-by: Huang Qi <[email protected]> As this breaks the systick Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Make mpfs_hart_index2id table modifiable by boo…
…tloader This is actually the same table as entrypoints, so just use the same data, which can be set before booting any of the harts Signed-off-by: Jukka Laitinen <[email protected]>
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Revert "[REVERTME] arch/risc-v/src/mpfs/mpfs_corespi.c: Hack around a…
… bug in nuttx nxsem_tickwait_uninterruptible bug" This reverts commit c9a794c.
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arch/risc-v/src/mpfs/mpfs_opensbi.c: Fix conflicting datatypes define…
…d by NuttX vs. opensbi Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_dsn: Correct serial number reading routine
- Fix retry counter handling and increase the maximum number of retries. - Add some parenthesis for clarity. - Change return type to signed int, as it may return -ETIMEDOUT - Correct comment for returned value Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: clean up ihc for rpmsg
This cleans the unnecessary flow control that's no longer needed. Probably the support for simultaneous MP and ACK changed the environment. Also reorganize the mpfs_opensbi_*.S so that the trap handler is easily relocated in the tlinker .ld file without the need to relocate the utils.S. This makes it easier to follow the jump into other segment, eg. zerodevice. Signed-off-by: Eero Nurkkala <[email protected]>
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mpfs_opensbi_utils.S: relocate OpenSBI into l2zerodevice
This loads the OpenSBI from eNVM into the zerodevice. Signed-off-by: Eero Nurkkala <[email protected]>
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opensbi: update to contain shrinked version
Update to have 2k smaller version of OpenSBI. Signed-off-by: Eero Nurkkala <[email protected]>
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Revert "opensbi: update to contain shrinked version"
This reverts commit 95e02b0.
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risc-v/mpfs: ihc: don't wait for a remote ack
RPMSG is associated with the use of HPWORK / LPWORK queues. After sending a message to the remote end (Linux), it waits for an ack before proceeding. Unfortunately this may take sometimes more than 0x3000 CLINT MTIME cycles. Ack waiting is also unnecessary: nothing is done with that information. Even worse, the net_lock() is also held during the blocked time so it blocks other network stacks that are unrelated to this. The logic is still maintained with the message present (MP) flag. No new message will be sent until that is cleared by the romote. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: clear L2 before use
SiFive document: "ECC Error Handling Guide" states: "Any SRAM block or cache memory containing ECC functionality needs to be initialized prior to use. ECC will correct defective bits based on memory contents, so if memory is not first initialized to a known state, then ECC will not operate as expected. It is recommended to use a DMA, if available, to write the entire SRAM or cache to zeros prior to enabling ECC reporting. If no DMA is present, use store instructions issued from the processor." Clean the cache at this early stage so no ECC errors will be flooding later. Signed-off-by: Eero Nurkkala <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Correct the DDR training dq/dqs stat…
…us check It was checking a wrong register for dq/dqs window size. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Don't auto-determine the write latency
It doesn't make sense to try to auto-determine write latency, it may pass with too low value. Keep the existing implementation if the write latency has been set to minimum value, otherwise just set it. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Correct memory test timeouts
Especially the write calibration must bail out if the memory test timeouts, otherwise the device will get stuck in running the memory test in sequence, and it will always timeout. Negative error value was also not properly returned from mpfs_mtc_test. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Make sure that DDRC is in reset when…
… starting the training Also move the DDRC clock enablement and reset to mpfs_init_ddr. This doesn't change the functionality, but is the cleaner place for it. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Add a simple prng for memory trainin…
…g code Implement the previously empty mpfs_ddr_rand with adapted "seiran128" code from https://github.com/andanteyk/prng-seiran This implements a non-secure prng, which is minimal in size. The DDR training doesn't need cryptographically secure prng, and linking in the NuttX crypto would increase the code size significantly for bootloaders. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Aug 28, 2023
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Commits on Aug 29, 2023
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arch/risc-v/src/mpfs: Sync some of the libero config macros with HSS …
…reference code Signed-off-by: Jukka Laitinen <[email protected]> Co-authored-by: Eero Nurkkala <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Re-write write calibration
Clean up the code and remove un-used global variables & structs Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Sep 4, 2023
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arch/risc-v/src/mpfs: Set USB DMA upper addr offset
Use a configuration register to set the upper address lines [37:32] for USB DMA engine. Signed-off-by: Jani Paalijarvi <[email protected]>
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Commits on Sep 6, 2023
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drivers/timers/pcf85263.c: Fix compilation
Add the missing semicolons Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Sep 11, 2023
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drivers/net: Add a management driver for ksz9477 ethernet switch
Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs: Add ksz9477 initialization
This adds initialization of the ksz9477 switch when used instead of a PHY, directly connected to SGMII Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Sep 12, 2023
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arch/risc-v/src/mpfs/mpfs_i2c.c: Clean up using priv->status and STOP…
… interrupts - There are occasional extra STOPs being sent due to an IP bug when using an FPGA based I2C. Add a flag "inflight" to mask out extra STOP interrupts when using the FPGA based implementation - There are no MPFS_I2C_ST_STOP_SENT irq's "initally". It is just already either success or still in progress Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Sep 13, 2023
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riscv/riscv_pmp.c: Improve NAPOT area validity checks
Check that the base address and region size are properly aligned with relation to each other. With NAPOT encoding the area base and size are not arbitrary, as when the size increases the amount of bits available for encoding the base address decreases.
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mpfs/mpfs_i2c.c: Replace 1 second timeout with Time-on-Air based timeout
Calculate how long an I2C transation will take in microseconds, and use this as the timeout for mpfs_i2c_sem_waitdone. The reason for doing this is not to keep an i2c bus reserved for the full 1 second timeout, if e.g. a sensor is not on the bus / is faulty and non-responsive. Reading the other sensors will be blocked for a relatively long time (1 second) in this case. This fixes such behavior.
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libs/libc: Fix a fatal bug in fread
Fix a bug the destination buffer is not updated. It is caused by the following commit. commit 5d8d5bf
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stdio/lib_libfread: Fix buffer overflow issue
If the gulp size in the stdio buffer the remaining user buffer size it will: - Corrupt memory in dest (user memory) and - Keep corrupting KERNEL memory via the stdio character buffer until the whole system crashes, as the 'remaining' count underflows This patch fixes this behavior.
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Commits on Sep 18, 2023
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binfmt/binfmt_execmodule: Copy filename if CONFIG_BUILD_KERNEL and ar…
…gv=NULL The 'filename' parameter comes from user space and cannot be accessed after calling ret = addrenv_select(binp->addrenv, &binp->oldenv); as it changes the address environment and 'filename' points to who knows where. In this case, calling nxtask_init(filename...) will cause a crash. Solve this by making a local copy before changing address environment IF argv = NULL. Why ? Because argv[0] contains the process name in this case and the argument vector is already copied into kernel memory, thus passing argv[0] to nxtask_init(argv[0]...) is safe.
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risc-v/mpfs: Add DMA buffer allocator for eMMC access
The MPFS eMMC DMA has some requirements that are only fulfilled by enabling separate DMA access buffers (FAT DMA buffers) and by forcing indirect access to the media via FAT_FORCE_INDIRECT. Why? Direct access to user buffers violates two things: - Buffer alignment is not ensured - Buffers are user memory (problematic in BUILD_KERNEL)
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Commits on Sep 25, 2023
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tools/ci: ensure removing python and openssl related commands
Signed-off-by: Petro Karashchenko <[email protected]>
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tools/ci: Unify the version print: command xxx --version
Signed-off-by: Xiang Xiao <[email protected]>
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tools/ci: Fix "flock: Command not found" on macOS
Signed-off-by: Xiang Xiao <[email protected]>
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tools: Switch riscv GCC to 12.3
GCC13 have compatibility issue with libcxx (need libcxx 17+). Please refer to: llvm/llvm-project#62396 Signed-off-by: Huang Qi <[email protected]>
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cibuild.sh: Using GCC from xPack for riscv
Signed-off-by: Huang Qi <[email protected]>
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Follow other risc-v based chips, and fix: ``` chip/rv32m1_irq.c: In function 'up_irqinitialize': Error: chip/rv32m1_irq.c:98:3: error: array subscript -2048 is outside array bounds of 'uint8_t[2147483647]' {aka 'unsigned char[2147483647]'} [-Werror=array-bounds] 98 | riscv_stack_color(g_intstacktop - intstack_size, intstack_size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In file included from /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_internal.h:40, from chip/rv32m1_irq.c:36: /github/workspace/sources/nuttx/arch/risc-v/src/common/riscv_common_memorymap.h:72:16: note: at offset -2048 into object 'g_intstacktop' of size [0, 2147483647] 72 | EXTERN uint8_t g_intstacktop[]; /* Initial top of interrupt stack */ | ^~~~~~~~~~~~~ cc1: all warnings being treated as errors ``` Signed-off-by: Huang Qi <[email protected]>
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espressif: Force cast param in libc stubs
Fix: ``` chip/esp_libc_stubs.c: In function '__retarget_lock_init': Error: chip/esp_libc_stubs.c:246:14: error: passing argument 1 of '_lock_init' from incompatible pointer type [-Werror=incompatible-pointer-types] 246 | _lock_init(lock); | ^~~~ | | | struct __lock ** chip/esp_libc_stubs.c:181:26: note: expected 'int *' but argument is of type 'struct __lock **' 181 | void _lock_init(_lock_t *lock) | ^ chip/esp_libc_stubs.c: In function '__retarget_lock_init_recursive': Error: chip/esp_libc_stubs.c:251:24: error: passing argument 1 of '_lock_init_recursive' from incompatible pointer type [-Werror=incompatible-pointer-types] 251 | _lock_init_recursive(lock); | ^~~~ | | | struct __lock ** chip/esp_libc_stubs.c:187:36: note: expected 'int *' but argument is of type 'struct __lock **' 187 | void _lock_init_recursive(_lock_t *lock) | ^ chip/esp_libc_stubs.c: In function '__retarget_lock_close': Error: chip/esp_libc_stubs.c:256:15: error: passing argument 1 of '_lock_close' from incompatible pointer type [-Werror=incompatible-pointer-types] 256 | _lock_close(&lock); | ^~~~~ | | | struct __lock ** chip/esp_libc_stubs.c:193:27: note: expected 'int *' but argument is of type 'struct __lock **' 193 | void _lock_close(_lock_t *lock) ``` Signed-off-by: Huang Qi <[email protected]>
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boards/riscv: Fix module linker target
Fix: ``` riscv-none-elf-ld: sotest.o: ABI is incompatible with that of the selected emulation: target emulation `elf64-littleriscv' does not match `elf32-littleriscv' riscv-none-elf-ld: failed to merge target specific data of file sotest.o ``` Signed-off-by: Huang Qi <[email protected]>
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boards/riscv: Add -melf64lriscv to 64bit USER_LDFLAGS/LDELFFLAGS
Signed-off-by: Xiang Xiao <[email protected]>
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arch/riscv: Move -mcmodel=medany from Make.defs to Toolchain.defs
to avoid the code duplication Signed-off-by: Xiang Xiao <[email protected]>
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Commits on Sep 26, 2023
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risc-v/mpfs: ihc: don't wait for master if it's already up
After rebooting this ihc client hart only, ihc will hang as it's waiting for the initial handshake that just won't be there. Detect this situation and let the rptun / ihc know the master is already up. This makes the RPMSG bus usable even after NuttX reboot, in case there's not much traffic. However, Linux is likely to mark the virtio queue broken if there's descent amount of traffic. This makes the bus no longer function. Also deny uninitialized early access for particular structs. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: emmcsd: deny unaligned access
Don't allow unaligned access with the DMA requests. Return -EFAULT in case the provided address is unaligned. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Oct 2, 2023
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mpfs/mpfs_corespi: Several speed optimizations to the FPGA driver
This is a collection of tweaks / optimizations to the driver to limit CPU usage as well as interrupt processing times. The changes are as follows: - setfrequency is now no-op if the frequency does not change. Accessing MPFS_SPI_CONTROL requires synchronization to the FIC domain, which takes unnecessary time if nothing changes - load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are only tested once (instead of for every word written in loop). - Disable the RX interrupt only once (again, FIC domain access is slow) - In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the whole RX FIFO, instead of trying to read it byte-by-byte
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risc-v/pgalloc.h: Add SHM area to riscv_uservaddr query
If the vaddr resides within the user's SHM, it is a user memory mapping.
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risc-v/riscv_addrenv.c: Fix bug where SHM area page tables are not freed
The SHM physically backed memory does not belong to the user process, but the page table containing the mapping does -> delete the page table memory regardless.
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Commits on Oct 3, 2023
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mm/kmap: Change kmm_user_map to kmm_map_user
Naming consistency wrt kmm_map_user_page
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Searching the current process mappings for kmappings is quite futile, do the search in the kernel's mappings instead.
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riscv/addrenv: Fix the user VMA end address
The end address was off by 1, making it overflow to 0 (u32 value).
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Commits on Oct 11, 2023
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[REVERTME] riscv_addrenc.c: Add more heap, if TLS_ALIGNED is set
The TLS alignment requires more room in the stack, which means more _initial_ heap is required to accomodate the stack. Why 2x TLS_MAXSTACK ? No idea. This is a temporary fix, like the +1 page extra above.
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riscv_addrenv_utils.c: Determine page table flags by type of vaddr
Use kernel page table flags if the mapped virtual address is in kernel space.
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riscv-v/pgalloc.h: Return kernel vaddr for kernel RAM paddr
All kernel memory is mapped paddr=vaddr, so it is trivial to give mapping for kernel memory. Only interesting region should be kernel RAM, so omit kernel ROM and don't allow re-mapping it.
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sched/assert.c: Print process name in assert dump
In addition to printing out the thread name (task name in flat mode), print the parent process's name as well. It is quite useful to know which process is the parent of a faulting thread, although this information can be read from the assert dump, in some cases the dump might be incomplete (due to e.g. stack corruption, which causes another exception and PANIC().)
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kmm_map.c: Fix call to gran_alloc
Provide the handle to gran_alloc, not pointer to handle.
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kmm_map.c: Fix user page mapping
User pages are mapped from the currently active address environment. If the process is running on a borrowed address environment, then the mapping should be created from there. This happens during (new) process creation only.
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kmm_map.c: Add way to test if addr is within kmap area or not
is_kmap_vaddr is added and used to test that a given (v)addr is actually inside the kernel map area. This gives a speed optimization for kmm_unmap, as it is no longer necessary to take the mm_map_lock to check if such a mapping exists; obviously if the address is not within the kmap area, it won't be in the list either.
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kmm_map.c: Remember to free the temporary 'pages' variable
The temp variable was freed only in error cases, but it needs to be freed in the happy case as well.
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kmm_map: Add function to map a single page of kernel memory
Mapping a physical page to a kernel virtual page is very simple and does not need the kernel vma list, just get the kernel addressable virtual address for the page.
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Commits on Oct 13, 2023
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risc-v/mpfs/opensbi: update opensbi to version 1.3.1
Version 1.3.1 is the latest tagged version. This patch prepares the required changes to make v1.3.1 work. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Oct 17, 2023
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mpfs/mpfs_entrypoints.c: Fix potential R_RISCV_JAL linker error
Change bgtz t0, mpfs_opensbi_prepare_hart to tail-call to ensure there will be no link time error due to the jump offset being too large.
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mpfs_ethernet.c: Fix possible NULL de-reference
Fix case where NULL is de-referenced via tx/rx buffer or descriptor. Only 1 queue is currently set up for each, so the indices 1,2,3 are not valid and should not be handled.
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mpfs_ethernet.c: Release tx descriptor and rx buffer properly
Instead of releasing rx descriptor twice and tx buffer twice.
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mpfs_head.S: Simplify clearing PMP
Initially clear PMP for all harts, this fixes random warm reset issues. Signed-off-by: Ville Juven <[email protected]>
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Commits on Oct 20, 2023
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arch/risc-v/src/mpfs/mpfs_ddr.c: Add read dq/dqs eye centering test
After read training, check also that the eye is centered properly. Sometimes after the training the width is long enough, but it is not centered. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Clean up the TXDLY verify step
Just verify that the delay for the selected clock != 0 Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_ddr.c: Fix CA training verify step
Corrections to CA training verify step. The original copied from HSS didn't make sense in all aspects: - The check is not per lane, so it should be out of the "for (lane_sel" loop. - The check wasn't proper. The expected outcome is just a vector of increasing numbers separated enough Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Oct 24, 2023
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riscv/riscv_pmp.c: fix broken TOR checks
PMPCFG_A_TOR region may have zero size. The pmp configuration currently fails for zero-sized TOR. This patch bypasses such a restriction. Also replace log2ceil with LOG2_CEIL from lib/math32.h. Signed-off-by: Eero Nurkkala <[email protected]>
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arch/risc-v: Remove unnecessary PMP kconfig options
These options are just wrong and a result of misunderstanding of the Polarfire SoC spec. There are no feature limitations in the CPU PMP implementation -> remove any configuration options added.
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arch/risc-v: Simplify pmp_check_region_attrs sanity-checks
For TOR: Any size and 4-byte aligned address is required For NA4: Only size 4 and 4-byte aligned address is good For NAPOT: Minimum size is 8 bytes, minimum base alignment is 8 bytes, and size must be power-of-two aligned with base This commit simplifies these checks and removes all the nonsense added by a misunderstanding of how the MPFS / Polarfire SoC's PMP works.
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Commits on Oct 25, 2023
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mpfs_opensbi: Remove mpfs_opensbi_pmp_setup
The PMP setup should be done in the board specific code, at a much earlier stage. Granting all access is a security risk anyway.
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mpfs_entrypoints.c: Open all memory from PMP for hart before booting
Open PMP before the hart payload starts to execute
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arch/mpfs: Add CONFIG_MPFS_BOARD_PMP option for PMP configuration
This adds option to do PMP configuration via mpfs_board_pmp_setup instead of just opening up everything. In this case, it is up to the specific board to implement the PMP configuration in whichever way it sees fit.
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Commits on Oct 30, 2023
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Exec: Support run exec in current task
There is a problem when vfork() calls execv() (or execl()) to start a new application: When the parent thread calls vfork() it receives and gets the pid of the vforked task, and not the pid of the desired execv'ed application. see issue apache#3334 Signed-off-by: yangyalei <[email protected]>
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sched/task_[posix]spawn: Simplify how spawn attributes are handled
Handle task spawn attributes as task spawn file actions are handled. Why? This removes the need for sched_lock() when the task is being spawned. When loading the new task from a file the scheduler can be locked for a VERY LONG time, in the order of hundreds of milliseconds! This is unacceptable for real time operation. Also fixes a latent bug in exec_module, spawn_file_actions is executed at a bad location; when CONFIG_ARCH_ADDRENV=y actions will point to the new process's address environment (as it is temporarily instantiated at that point). Fix this by moving it to after addrenv_restore.
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Commits on Oct 31, 2023
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arch/risc-v/src/mpfs/mpfs_serial.c: Allow switching uart output to co…
…nsole off By setting "isconsole" to false, mpfs_serial stops outputting to console. This can be used to disable output to debug console in low level. Signed-off-by: Jukka Laitinen <[email protected]>
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risc-v/mpfs: i2c: prevent out of bounds read access
priv->msgid may grow past its boundaries, causing struct i2c_msg_s *msg = &priv->msgv[priv->msgid] to read data out of boundaris. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Nov 9, 2023
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risc-v/mpfs: add tamper detection support
This adds support for detecting various tamper events. The interrupt handler makes noise at every detection. Perhaps easiest test is to attach JTAG debugger. TAMPER_TESTS -define has some nonexisting (not in repos) calls, perhaps could remove it alltogether. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Nov 13, 2023
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risc-v/mpfs: tamper: refine tests
Use only tests that will trigger a tamper event. Leave other tests outside. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Nov 15, 2023
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risc-v/mpfs: ihc: cleanup DEBUGASSERTs and reboot
Replace DEBUGASSERTs with sanity checks. DEBUGASSERT()s are not necessarily enabled at all, thus risking the functionality especially in that case. Remove PANICs as well. Don't enable the ihc irq too early. If enabled, and the master is already up, the irq is being issued so that the system gets stuck or is severely slowed down. Master may be already if this NuttX hart is rebooted, for example. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Nov 16, 2023
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sched/sem_holder.c: When accessing SEM_WAITLIST, use holder's addrenv
If the semaphore is shared, the holder has put its own mmapped address to pholder->sem. This means we must switch to the holder's address environment when going through the held semaphores list. A better option would be to get the kernel mapped address for the semaphore's physical page, but that mechanism is not functional yet. This fixes a full system crash when CONFIG_PRIORITY_INHERITANCE=y and CONFIG_BUILD_KERNEL=y and user makes shared semaphore via: int semfd = shm_open("sem", O_CREAT | O_RDWR, 0666); sem_t *sem = mmap(0, sizeof(sem_t), PROT_READ | PROT_WRITE, MAP_SHARED, semfd, 0);
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Commits on Nov 29, 2023
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mpfs/mpfs_corespi.c: Round up divider to prevent overlock of SPI
The divider should be rounded to the next full integer to ensure that the resulting SPI frequency is <= target frequency, i.e. the SPI is not overclocked.
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risc-v/mpfs: tamper: fix a typo
Caught out means something else that was intended. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Nov 30, 2023
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risc-v/mpfs: usb: fix fierce cpu polling if remote closes
If the remote end just closes an endpoint and no longer handles it, the system is prone to intensive cpu polling via mpfs_write_tx_fifo() especially if the device side doesn't know a thing about what the remote did. Fix this by marking the EP as dead, which will skip all writes causing unnecessary polling. The EP is back in business if the remote end sends some data (rx) or the connection is re-established. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Dec 1, 2023
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risc-v/mpfs: usb: don't try nonexistent ep int flags
Currently the irq handler checks many reserved bits, which is a waste of resources: 1. pending_rx_ep bit 0 is reserved (always 0) 2. pending_rx_ep and pending_tx_ep have only bits 1, 2, 3 and 4 defined, no need to scan MPFS_USB_NENDPOINTS (9) bits as the rest are reserved Fix this by checking only the relevant bits. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Dec 5, 2023
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net: rpmsgdrv.c: prevent potential danger
Provide support for NET_RPMSG_TRANSFER only: "It is recommended to drop all messages with commands other than NET_RPMSG_TRANSFER in function net_rpmsg_drv_ept_cb() of the flight controller." Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Dec 8, 2023
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mm/kmap: Finalize kmap implementation for RISC-V
After this, RISC-V fully supports the kmap interface. Due to the current design limitations of having only a single L2 table per process, the kernel kmap area cannot be mapped via any user page directory, as they do not contain the page tables to address that range. So a "kernel address environment" is added, which can do the mapping. The mapping is reflected to every process as only the root page directory (L1) is copied to users, which means every change to L2 / L3 tables will be seen by every user.
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Commits on Dec 13, 2023
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riscv_pmp.c: Revert LOG2_CEIL back to run-time log2ceil function
The macro LOG2_CEIL is intended to be used in the pre-processor phase. If used run-time it will generate a massive amount of extra code (~3.5K) which is a problem, as the PMP configuration is quite often executed from a first stage bootloader with a limited amount of code memory. Code size differences pre- and post: Memory region Used Size Region Size %age Used envm: 112064 B 112384 B 99.72% Memory region Used Size Region Size %age Used envm: 108952 B 112384 B 96.95%
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[REVERTME] riscv/arch_elf.c: Handle PCREL_HI20/LO12_I/S relocations c…
…orrectly [REVERTME] This patch is a stripped version from upstream, there are too many changes to the changed modules (would need to pull dozens of commits) so only the RISC-V elf linker is updated. There is a problem with the current elf loader for risc-v: when a pair of PCREL_HI20 / LO12 relocations are encountered, it is assumed that these will follow each other immediately, as follows: label: auipc a0, %pcrel_hi(symbol) // R_RISCV_PCREL_HI20 load/store a0, %pcrel_lo(label)(a0) // R_RISCV_PCREL_LO12_I/S With this assumption, the hi/lo relocations are both done when a hi20 relocation entry is encountered, first to the current instruction (addr) and to the next instruction (addr + 4). However, this assumption is wrong. There is nothing in the elf relocation specification[1] that mandates this. Thus, the hi/lo relocation always needs to first fixup the hi-part, and when the lo-part is encountered, it needs to find the corresponding hi relocation entry, via the given "label". This necessitates (re-)visiting the relocation entries for the current section as well as looking for "label" in the symbol table. The NuttX elf loader does not allow such operations to be done in the machine specific part, so this patch fixes the relocation issue by introducing an architecture specific cache for the hi20 relocation and symbol table entries. When a lo12 relocation is encountered, the cache can be consulted to find the hi20 part. [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
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Commits on Dec 14, 2023
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fix MPFS_ETHMAC_LP/HPWORK flags
Set HPWORK as default workqueue for eth ISR work
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Commits on Dec 15, 2023
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risc-v/mpfs: emmcsd: enforce HS DDR mode
Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now. The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Dec 19, 2023
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risc-v/mpfs: ddr: lock segmentation registers
Set the LOCKED bit when the final ddr segmentatition is in place. Otherwise the system is prone to potential security issues if the config is altered later. Once the LOCKED bit is set, the register may no longer be changed. Signed-off-by: Eero Nurkkala <[email protected]>
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risc-v/mpfs: i2c: perform sanity checks
Replace risky DEBUGASSERT()s with real sanity checks. Also, do a few more checks as the system might occasionally fire an interrupt if the system has been restarted while in middle of an i2c transaction. Yet, modify i2c_transfer() function so that up_disable_irq() is always called at the end to better prevent ill-timed irqs. Signed-off-by: Eero Nurkkala <[email protected]>
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Commits on Dec 20, 2023
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drivers/net/ksz9477: Add simple port-based static VLAN configuration
Add a static port-based VLAN configuration for KSZ9477 switch. This doesn't use the VLAN tagging, but is a switch's internal mechanism to simply configure if the packet forwarding is allowed from one port to another. Signed-off-by: Jukka Laitinen <[email protected]>
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libs/log2ceil: Move implementation of log2ceil to a common place
Move log2ceil from riscv_pmp to libc. Also, implement log2floor for completeness. These are the run-time alternative to the compile-time macros.
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mpfs_usb.c: Use kernel memory instead of user memory for DMA
DMA directly to user (virtual) memory won't work, as the DMA engine(s) don't do address translations, i.e. they require a physical address. Using kernel heap is fine as it is mapped vaddr=paddr. Also, the USB DMA engine does not have any alignment requirements.
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mpfs_ethernet.c: Remove DMA_ENABLE hack
The hack just opens the entire SoC memory unconditionally, which is not a good idea. Test features can be used ad-hoc, they don't need to be supported by the build.
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Commits on Dec 21, 2023
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fs/fat: Fix number of data clusters usable for fat driver
Fix the issue where fat driver is not using the last two clusters in the file system. The fat parameter fs->fs_nclusters is the maximum number of data clusters; this doesn't include the two in the beginning. Many checks in the fat driver treat the fs->fs_nclusters-1 as being the last accessible cluster, which is not right, the last accessible one is actually this number + 2 when the cluster count includes the two first ones. Normally this is not an issue when writes are being done through the same driver, the last two clusters are just never used. But if the filesystem is modified by external driver, for example with a populated fat created with PC, or modifying the FS via USB-MSC, this leads to the fat driver not being able to read anything that uses the last two clusters. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Jan 8, 2024
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build.yml: Modify the build config
Remove unnecessary junk, just build icicle (we don't care about the rest)
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build.yml: Add ssrc board matrix for arm and risc-v
Don't use the upstream build targets
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Commits on Jan 10, 2024
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mpfs_mpu: Add driver to set MPUCFG registers
MPUCFG registers are used to enforce memory protection for DMA master devices.
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Commits on Jan 11, 2024
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mpfs_usb.c: Remove PMPCFG configuration from the driver
This is not the right place to modify DMA memory protection values. Why not? These are designed to protect other AMP mode instances. Opening the entire SoC's memory for the USB DMA kind of defeats this purpose. Also, the driver cannot know how to configure these registers correctly, only opening up the whole SoC "works".
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mpfs_mpucfg.c: Add mpfs_mpu_lock()
Add method to lock an MPUCFG entry. Locking means the value of the register cannot be changed until the SoC is reset.
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Commits on Jan 15, 2024
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arch/risc-v/src/mpfs/mpfs_i2c.c: Clear I2C_CTRL bits when initializin…
…g/deinitializing bus Ensure that there are no pending state or interrupts in the i2c controller. This removes errors caused by deinitialize/initialize sequences in error cases. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Add more error status codes
Add more error status codes to help debugging in the future. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Correct i2c reset / error recovery
- Use mpfs_i2c_deinit+mpfs_i2c_init sequence to re-initialize i2c block - Use the i2c mutex to protect the reset; in case there are several devices on the same bus, and one of them resets the bus, reset must not occur in the middle of another device's transfer. - Move irq attach to the i2c_init as the irq detach is in i2c_deinit Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Add more i2cerr traces
Add sanity checks for debugging possible errors in the driver. Signed-off-by: Jukka Laitinen <[email protected]>
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arch/risc-v/src/mpfs/mpfs_i2c.c: Recover i2c from pending transaction…
…s in warm boot Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Jan 17, 2024
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arch/risc-v/src/mpfs/mpfs_irq.c: Fix up_irqinitialize for warm reboot
It is possible that a PLIC IRQ is claimed but not completed at warm reset. This occurs at least if there is a fault in the middle of irq handler execution. To recover from such situation, we can complete all IRQ:s in PLIC; this completes any already claimed IRQ, but has no effect on IRQs which are not claimed or not enabled. Signed-off-by: Jukka Laitinen <[email protected]>
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Commits on Jan 23, 2024
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DRAFT: Add a new arm64 family of boards, jetson
Signed-off-by: Jukka Laitinen <[email protected]>
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Add ARCH_CHIP_JETSON, ARCH_BOARD_JETSON_NANO and ARCH_CORTEX_A78AE to…
… KConfigs Signed-off-by: Jukka Laitinen <[email protected]>
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Make a draft board configuration for Orin NX / Jetson
Signed-off-by: Jukka Laitinen <[email protected]>
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