arch/arm64/src/imx9/imx9_lpspi.c: Fix 9-16 bit transfers and dcache i… #304
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arch/arm64/src/imx9/imx9_lpspi.c
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| @@ -1464,7 +1472,7 @@ static void imx9_lpspi_exchange(struct spi_dev_s *dev, | |||
| /* Flush the RX data to ram */ | |||
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| up_invalidate_dcache((uintptr_t)priv->rxbuf, | |||
| (uintptr_t)priv->rxbuf + nbytes); | |||
| (uintptr_t)priv->rxbuf + DCACHE_ALIGN_UP(nbytes)); | |||
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Handling the cache line alignment should not be the responsibility of the SPI driver, the cache operation must handle this. Does this not work as expected ?
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Invalidating a non-aligned area does clean and invalidate, which would be wrong.
But, this memory area is only used as rx buffer so it is never dirty. So you are right, aligning is not necessary in this case. In general it can't be said that aligning wouldn't be the responsibility of the driver... I was a bit hasty here while trying to get things working :)
I'll remove the unnecessary change. Btw. to optimize, we could move the initial invalidate to be only after the buffer allocation, it shouldn't be needed on every transfer?
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The buffer start and end must be aligned, this is guaranteed by the DMA safe buffer allocator. I don't know why there are two invalidate operations per transfer, 1 is enough.
The original driver (copy&pasted) did not use DMA safe buffers, so its functionality was unpredictable, maybe some kind of remnant from that.
I think we should remove the other invalidate at line 1393 completely.
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I think we should remove the other invalidate at line 1393 completely.
I addressed this with another patch. Initial invalidation should be done after allocation, to make sure that cache lines are not dirty before first transfers.
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Signed-off-by: Jukka Laitinen <[email protected]>
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There is no need to invalidate the RX buffer before every transfer. It is never gets dirty, so it is good to invalidate initially after allocation, and after each transfer. Signed-off-by: Jukka Laitinen <[email protected]>
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