Added de10lite board definition file to platforms

platforms/de10lite.py

@@ -0,0 +1,106 @@
+# This file is Copyright (c) 2019 msloniewski <[email protected]>
+# License: BSD
+
+from litex.build.generic_platform import *
+from litex.build.altera import AlteraPlatform
+from litex.build.altera.programmer import USBBlaster
+
+
+_io = [
+    ("clk10", 0, Pins("N5"), IOStandard("3.3-V LVTTL")),
+    ("clk50", 0, Pins("P11"), IOStandard("3.3-V LVTTL")),
+    ("clk50", 1, Pins("N14"), IOStandard("3.3-V LVTTL")),
+
+    ("serial", 0,
+        Subsignal("tx", Pins("V10"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
+        Subsignal("rx", Pins("W10"), IOStandard("3.3-V LVTTL"))  # JP1 GPIO[1]
+    ),
+
+    ("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 2, Pins("A10"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 3, Pins("B10"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 4, Pins("D13"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 5, Pins("C13"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 6, Pins("E14"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 7, Pins("D14"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 8, Pins("A11"), IOStandard("3.3-V LVTTL")),
+    ("user_led", 9, Pins("B11"), IOStandard("3.3-V LVTTL")),
+
+    ("user_btn", 0, Pins("B8"), IOStandard("3.3-V LVTTL")),
+    ("user_btn", 1, Pins("A7"), IOStandard("3.3-V LVTTL")),
+
+    ("user_sw", 0, Pins("C10"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 1, Pins("C11"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 2, Pins("D12"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 3, Pins("C12"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 4, Pins("A12"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 5, Pins("B12"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 6, Pins("A13"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 7, Pins("A14"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 8, Pins("B14"), IOStandard("3.3-V LVTTL")),
+    ("user_sw", 9, Pins("F15"), IOStandard("3.3-V LVTTL")),
+
+    # 7-segment displays
+    ("seven_seg", 0, Pins("C14 E15 C15 C16 E16 D17 C17 D15"), IOStandard("3.3-V LVTTL")),
+    ("seven_seg", 1, Pins("C18 D18 E18 B16 A17 A18 B17 A16"), IOStandard("3.3-V LVTTL")),
+    ("seven_seg", 2, Pins("B20 A20 B19 A21 B21 C22 B22 A19"), IOStandard("3.3-V LVTTL")),
+    ("seven_seg", 3, Pins("F21 E22 E21 C19 C20 D19 E17 D22"), IOStandard("3.3-V LVTTL")),
+    ("seven_seg", 4, Pins("F18 E20 E19 J18 H19 F19 F20 F17"), IOStandard("3.3-V LVTTL")),
+    ("seven_seg", 5, Pins("J20 K20 L18 N18 M20 N19 N20 L19"), IOStandard("3.3-V LVTTL")),
+
+
+    ("gpio_0", 0,
+        Pins("V10 W10 V9 W9 V8 W8 V7 W7 W6 V5 W5 AA15 AA14 W13 W12 AB13 AB12 Y11 AB11 W11 AB10 AA10 AA9 Y8 AA8 Y7 AA7 Y6 AA6 Y5 AA5 Y4 AB3 Y3 AB2 AA2"),
+        IOStandard("3.3-V LVTTL")
+    ),
+    ("gpio_1", 0,
+        Pins("AB5 AB6 AB7 AB8 AB9 Y10 AA11 AA12 AB17 AA17 AB19 AA19 Y19 AB20 AB21 AA20 F16"),
+        IOStandard("3.3-V LVTTL")
+    ),
+
+    ("vga_out", 0,
+        Subsignal("hsync_n", Pins("N3")),
+        Subsignal("vsync_n", Pins("N1")),
+        Subsignal("r", Pins("AA1 V1 Y2 Y1")),
+        Subsignal("g", Pins("W1 T2 R2 R1")),
+        Subsignal("b", Pins("P1 T1 P4 N2")),
+        IOStandard("3.3-V LVTTL")
+    ),
+
+    ("sdram_clock", 0, Pins("L14"), IOStandard("3.3-V LVTTL")),
+    ("sdram", 0,
+        Subsignal("a", Pins("U17 W19 V18 U18 U19 T18 T19 R18 P18 P19 T20 P20 R20")),
+        Subsignal("ba", Pins("T21 T22")),
+        Subsignal("cs_n", Pins("U20")),
+        Subsignal("cke", Pins("N22")),
+        Subsignal("ras_n", Pins("U22")),
+        Subsignal("cas_n", Pins("U21")),
+        Subsignal("we_n", Pins("V20")),
+        Subsignal("dq", Pins("Y21 Y20 AA22 AA21 Y22 W22 W20 V21 P21 J22 H21 H22 G22 G20 G19 F22")),
+        Subsignal("dm", Pins("V22 J21")),
+        IOStandard("3.3-V LVTTL")
+    ),
+
+    ("accelerometer", 0,
+        Subsignal("int1", Pins("Y14")),
+        Subsignal("int1", Pins("Y13")),
+        Subsignal("mosi", Pins("V11")),
+        Subsignal("miso", Pins("V12")),
+        Subsignal("clk", Pins("AB15")),
+        Subsignal("cs_n", Pins("AB16")),
+        IOStandard("3.3-V LVTTL")
+    )
+]
+
+
+class Platform(AlteraPlatform):
+    default_clk_name = "clk50"
+    default_clk_period = 1e9/50e6
+    create_rbf = False
+
+    def __init__(self):
+        AlteraPlatform.__init__(self, "10M50DAF484C7G", _io)
+
+    def create_programmer(self):
+        return USBBlaster()

targets/de10lite/Makefile.mk

@@ -0,0 +1,56 @@
+# de10lite targets
+
+ifneq ($(PLATFORM),pipistrello)
+	$(error "Platform should be de10lite when using this file!?")
+endif
+
+# Settings
+DEFAULT_TARGET = base
+TARGET ?= $(DEFAULT_TARGET)
+
+PROG_PORT ?= /dev/ttyUSB0
+COMM_PORT ?= /dev/ttyUSB1
+BAUD ?= 115200
+
+# Image
+image-flash-$(PLATFORM):
+	@echo "Unsupported"
+	@false
+
+# Gateware
+gateware-load-$(PLATFORM):
+	quartus_pgm -z --mode=JTAG  -c USB-Blaster --operation = "p;$(TARGET_BUILD_DIR)/gateware/top.sof@1"
+
+gateware-flash-$(PLATFORM):
+	@echo "Unsupported"
+	@false
+
+# Firmware
+firmware-load-$(PLATFORM):
+	@echo "Unsupported."
+	@false
+
+firmware-flash-$(PLATFORM):
+	@echo "Unsupported."
+	@false
+
+firmware-connect-$(PLATFORM):
+	@echo "Unsupported."
+	@false
+
+firmware-clear-$(PLATFORM):
+	@echo "FIXME: Unsupported?."
+	@false
+
+# Bios
+bios-flash-$(PLATFORM):
+	@echo "Unsupported."
+	@false
+
+# Extra commands
+help-$(PLATFORM):
+	@true
+
+reset-$(PLATFORM):
+	@echo "Unsupported."
+	@false

targets/de10lite/base.py

@@ -0,0 +1,94 @@
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import de10lite
+
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+
+from litedram.modules import IS42S16320
+from litedram.phy import GENSDRPHY
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_sys    = ClockDomain()
+        self.clock_domains.cd_sys_ps = ClockDomain()
+        self.clock_domains.cd_vga    = ClockDomain(reset_less=True)
+
+        # # #
+
+        # Clk / Rst
+        clk50 = platform.request("clk50")
+        platform.add_period_constraint(clk50, 1e9/50e6)
+
+        # PLL
+        pll_locked  = Signal()
+        pll_clk_out = Signal(6)
+        self.specials += \
+            Instance("ALTPLL",
+                p_BANDWIDTH_TYPE         = "AUTO",
+                p_CLK0_DIVIDE_BY         = 1,
+                p_CLK0_DUTY_CYCLE        = 50,
+                p_CLK0_MULTIPLY_BY       = 1,
+                p_CLK0_PHASE_SHIFT       = "0",
+                p_CLK1_DIVIDE_BY         = 1,
+                p_CLK1_DUTY_CYCLE        = 50,
+                p_CLK1_MULTIPLY_BY       = 1,
+                p_CLK1_PHASE_SHIFT       = "-10000",
+                p_CLK2_DIVIDE_BY         = 2,
+                p_CLK2_DUTY_CYCLE        = 50,
+                p_CLK2_MULTIPLY_BY       = 1,
+                p_CLK2_PHASE_SHIFT       = "0",
+                p_COMPENSATE_CLOCK       = "CLK0",
+                p_INCLK0_INPUT_FREQUENCY = 20000,
+                p_OPERATION_MODE         = "NORMAL",
+                i_INCLK                  = clk50,
+                o_CLK                    = pll_clk_out,
+                i_CLKENA                 = 0x3f,
+                i_EXTCLKENA              = 0xf,
+                i_FBIN                   = 1,
+                i_PFDENA                 = 1,
+                i_PLLENA                 = 1,
+                o_LOCKED                 = pll_locked,
+            )
+        self.comb += [
+            self.cd_sys.clk.eq(pll_clk_out[0]),
+            self.cd_sys_ps.clk.eq(pll_clk_out[1]),
+            self.cd_vga.clk.eq(pll_clk_out[2])
+        ]
+        self.specials += [
+            AsyncResetSynchronizer(self.cd_sys,    ~pll_locked),
+            AsyncResetSynchronizer(self.cd_sys_ps, ~pll_locked),
+            AsyncResetSynchronizer(self.cd_vga,    ~pll_locked)
+        ]
+
+        # SDRAM clock
+        self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCSDRAM):
+    def __init__(self, sys_clk_freq=int(50e6), **kwargs):
+        assert sys_clk_freq == int(50e6)
+        platform = de10lite.Platform()
+
+        # SoCSDRAM ---------------------------------------------------------------------------------
+        SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform)
+
+        # SDR SDRAM --------------------------------------------------------------------------------
+        if not self.integrated_main_ram_size:
+            self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
+            sdram_module = IS42S16320(self.clk_freq, "1:1")
+            self.register_sdram(self.sdrphy,
+                geom_settings   = sdram_module.geom_settings,
+                timing_settings = sdram_module.timing_settings)
+
+
+SoC = BaseSoC