Fix build warnings

src/DRAMPower/DRAMPower/command/Command.h

@@ -33,19 +33,19 @@ class Command {
 public:
     Command() = default;
 	Command(timestamp_t timestamp, CmdType type, TargetCoordinate targetCoord = {}, const uint8_t * data = nullptr, std::size_t sz_bits = 0)
-		: type(type)
+        : timestamp(timestamp)
+		, type(type)
 		, targetCoordinate(targetCoord)
-        , timestamp(timestamp)
 		, data(data)
 		, sz_bits(sz_bits)
 	{};
 
 public:
+    timestamp_t timestamp = 0;
+    CmdType type;
     TargetCoordinate targetCoordinate;
 
-    CmdType type;
 
-    timestamp_t timestamp = 0;
     const uint8_t * data = 0x00; // ToDo: buffer{ptr, sz} / TLM Standard
 	std::size_t sz_bits;
     //uint64_t burstLength;

src/DRAMPower/DRAMPower/command/Pattern.h

@@ -7,6 +7,7 @@
 #include <cassert>
 #include <unordered_map>
 #include <vector>
+#include <limits.h>
 
 namespace DRAMPower {
 namespace pattern_descriptor {
@@ -135,11 +136,12 @@ inline bool applyBitSpec(
         std::bitset<32> bank_group_bits(cmd.targetCoordinate.bankGroup);
 
         std::size_t n = pattern.size() - 1;
+        static_assert(std::numeric_limits<decltype(n)>::is_signed == false, "std::size_t must be unsigned");
 
         assert(n < 64);
 
         for (const auto descriptor : pattern) {
-            assert(n >= 0);
+            // assert(n >= 0); // std::size_t is unsigned
 
             switch (descriptor) {
             case H:

src/DRAMPower/DRAMPower/data/energy.h

@@ -59,7 +59,7 @@ struct energy_t
 	std::vector<energy_info_t> bank_energy;
 	energy_info_t total_energy(); // TODO rename
 	void to_json(json_t &j) const;
-	constexpr inline const char * const get_Bank_energy_keyword() const
+	constexpr inline const char * get_Bank_energy_keyword() const
 	{
 		return "BankEnergy";
 	}

src/DRAMPower/DRAMPower/dram/dram_base.h

@@ -31,19 +31,20 @@ class dram_base {
 
 public:
     commandCount_t commandCount;
-protected:
-    uint64_t lastPattern;
-    PatternEncoder encoder;
 private:
     commandRouter_t commandRouter;
     commandPatternMap_t commandPatternMap;
+protected:
+    PatternEncoder encoder;
+    uint64_t lastPattern;
+private:
     implicitCommandList_t implicitCommandList;
     timestamp_t last_command_time;
 
 public:
     dram_base(PatternEncoderOverrides encoderoverrides)
         : commandCount(static_cast<std::size_t>(CommandEnum::COUNT), 0)
-        , commandRouter(static_cast<std::size_t>(CommandEnum::COUNT), [](const Command& cmd) {})
+        , commandRouter(static_cast<std::size_t>(CommandEnum::COUNT), [](const Command&) {})
         , commandPatternMap(static_cast<std::size_t>(CommandEnum::COUNT), commandPattern_t {})
         , encoder(encoderoverrides)
         , lastPattern(0)
@@ -98,33 +99,33 @@ class dram_base {
             [](const auto& lhs, const auto& rhs) { return lhs.first < rhs.first; });
 
         implicitCommandList.emplace(upper, entry);
-    };
+    }
 
     template <CommandEnum cmd, typename Func>
     void routeCommand(Func&& func)
     {
         assert(commandRouter.size() > static_cast<std::size_t>(cmd));
         this->commandRouter[static_cast<std::size_t>(cmd)] = func;
-    };
+    }
 
     template <CommandEnum cmd_type>
     void registerPattern(std::initializer_list<pattern_descriptor::t> pattern)
     {
         this->commandPatternMap[static_cast<std::size_t>(cmd_type)] = commandPattern_t(pattern);
-    };
+    }
 
     template <CommandEnum cmd_type>
     void registerPattern(const commandPattern_t &pattern)
     {
         this->commandPatternMap[static_cast<std::size_t>(cmd_type)] = pattern;
-    };
+    }
 
     const commandPattern_t& getPattern(CmdType cmd_type)
     {
         return this->commandPatternMap[static_cast<std::size_t>(cmd_type)];
-    };
+    }
 
-    const std::size_t implicitCommandCount() const { return this->implicitCommandList.size(); };
+    std::size_t implicitCommandCount() const { return this->implicitCommandList.size(); };
 
     void processImplicitCommandQueue(timestamp_t timestamp)
     {

src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h

@@ -77,8 +77,8 @@ class MemSpecDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecDDR4>
 
     uint64_t timeToCompletion(CmdType type) override;
 
-	unsigned numberOfBankGroups;
-	unsigned numberOfRanks;
+	uint64_t numberOfBankGroups;
+	uint64_t numberOfRanks;
 
 	double vddq;
 

src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h

@@ -38,9 +38,9 @@ namespace DRAMPower {
         uint64_t timeToCompletion(CmdType type) override;
 
 
-        unsigned numberOfBankGroups;
-        unsigned banksPerGroup;
-        unsigned numberOfRanks;
+        uint64_t numberOfBankGroups;
+        uint64_t banksPerGroup;
+        uint64_t numberOfRanks;
 
         double vddq;
 
@@ -94,9 +94,9 @@ namespace DRAMPower {
         };
 
         struct DataRateSpec {
-            uint32_t commandBusRate;
-            uint32_t dataBusRate;
-            uint32_t dqsBusRate;
+            uint64_t commandBusRate;
+            uint64_t dataBusRate;
+            uint64_t dqsBusRate;
         };
 
         struct BankWiseParams

src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h

@@ -37,9 +37,9 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
 	~MemSpecLPDDR4() = default;
 	uint64_t timeToCompletion(CmdType type) override;
 
-    unsigned numberOfBankGroups;
-    unsigned banksPerGroup;
-    unsigned numberOfRanks;
+    uint64_t numberOfBankGroups;
+    uint64_t banksPerGroup;
+    uint64_t numberOfRanks;
 
 	double vddq;
 
@@ -110,7 +110,7 @@ class MemSpecLPDDR4 final : public MemSpec<DRAMUtils::MemSpec::MemSpecLPDDR4>
 		// ACT Standby power factor
 		double bwPowerFactRho;
 		// Self-Refresh power factor
-		uint64_t bwPowerFactSigma;
+		double bwPowerFactSigma;
 		// Whether PASR is enabled ( true : enabled )
 		bool flgPASR;
 		// PASR mode utilized (int 0-7)

src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h

@@ -42,9 +42,9 @@ namespace DRAMPower {
         uint64_t timeToCompletion(CmdType type) override;
 
 
-        unsigned numberOfBankGroups;
-        unsigned banksPerGroup;
-        unsigned numberOfRanks;
+        uint64_t numberOfBankGroups;
+        uint64_t banksPerGroup;
+        uint64_t numberOfRanks;
         std::size_t perTwoBankOffset = 8;
         BankArchitectureMode bank_arch;
         bool wckAlwaysOnMode;

src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp

@@ -9,8 +9,12 @@
 namespace DRAMPower {
 
     DDR4::DDR4(const MemSpecDDR4 &memSpec)
-		: memSpec(memSpec)
-		, ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
+        : dram_base<CmdType>({
+            {pattern_descriptor::V, PatternEncoderBitSpec::H},
+            {pattern_descriptor::X, PatternEncoderBitSpec::H},
+          })
+        , memSpec(memSpec)
+        , ranks(memSpec.numberOfRanks, {(std::size_t)memSpec.numberOfBanks})
         , readBus(
             memSpec.bitWidth * memSpec.numberOfDevices, memSpec.dataRate,
              util::Bus::BusIdlePatternSpec::H, util::Bus::BusInitPatternSpec::H
@@ -21,19 +25,15 @@ namespace DRAMPower {
         )
         , cmdBusWidth(27)
         , cmdBusInitPattern((1<<cmdBusWidth)-1)
+        , readDQS_(2, true)
+        , writeDQS_(2, true)
         , commandBus(
             cmdBusWidth, 1,
             util::Bus::BusIdlePatternSpec::H,
             util::Bus::burst_t(cmdBusWidth, cmdBusInitPattern)
         )
-        , readDQS_(2, true)
-        , writeDQS_(2, true)
         , prepostambleReadMinTccd(memSpec.prePostamble.readMinTccd)
         , prepostambleWriteMinTccd(memSpec.prePostamble.writeMinTccd)
-        , dram_base<CmdType>({
-            {pattern_descriptor::V, PatternEncoderBitSpec::H},
-            {pattern_descriptor::X, PatternEncoderBitSpec::H},
-        })
 	{
         // In the first state all ranks are precharged
         //for (auto &rank : ranks) {
@@ -166,24 +166,25 @@ namespace DRAMPower {
     )
     {
         // TODO: If simulation finishes in read/write transaction the postamble needs to be substracted
-        uint64_t minTccd = prepostambleWriteMinTccd;
+        // uint64_t minTccd = prepostambleWriteMinTccd; // Todo use minTccd
         uint64_t *lastAccess = &rank.lastWriteEnd;
         uint64_t diff = 0;
 
         if(read)
         {
             lastAccess = &rank.lastReadEnd;
-            minTccd = prepostambleReadMinTccd;
+            // minTccd = prepostambleReadMinTccd;
         }
 
-        diff = timestamp - *lastAccess;
-        *lastAccess = timestamp + length;
-
-        if(diff < 0)
+        assert(timestamp >= *lastAccess);
+        if(timestamp < *lastAccess)
         {
             std::cout << "[Error] PrePostamble diff is negative. The last read/write transaction was not completed" << std::endl;
             return;
         }
+        diff = timestamp - *lastAccess;
+        *lastAccess = timestamp + length;
+
         //assert(diff >= 0);
 
         // Pre and Postamble seamless
@@ -255,26 +256,22 @@ namespace DRAMPower {
         assert(this->ranks.size()>cmd.targetCoordinate.rank);
         auto & rank = this->ranks[cmd.targetCoordinate.rank];
 
-        switch (cmd.type) {
-            case CmdType::RD:
-            case CmdType::RDA:
-                length = cmd.sz_bits / readBus.get_width();
-                if ( length != 0 )
-                {
-                    readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
-                }
-                else
-                {
-                    length = memSpec.burstLength; // Use default burst length
-                    // Cannot load readBus with data. TODO toggling rate
-                }
-                readDQS_.start(cmd.timestamp);
-                readDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
-                handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, true);
-                handleInterfaceOverrides(length, true);
-                break;
-            case CmdType::WR:
-            case CmdType::WRA:
+        if (cmd.type == CmdType::RD || cmd.type == CmdType::RDA) {
+            length = cmd.sz_bits / readBus.get_width();
+            if ( length != 0 )
+            {
+                readBus.load(cmd.timestamp, cmd.data, cmd.sz_bits);
+            }
+            else
+            {
+                length = memSpec.burstLength; // Use default burst length
+                // Cannot load readBus with data. TODO toggling rate
+            }
+            readDQS_.start(cmd.timestamp);
+            readDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
+            handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, true);
+            handleInterfaceOverrides(length, true);
+        } else if (cmd.type == CmdType::WR || cmd.type == CmdType::WRA) {
                 length = cmd.sz_bits / writeBus.get_width();
                 if ( length != 0 )
                 {
@@ -289,8 +286,7 @@ namespace DRAMPower {
                 writeDQS_.stop(cmd.timestamp + length / memSpec.dataRate);
                 handlePrePostamble(cmd.timestamp, length / memSpec.dataRate, rank, false);
                 handleInterfaceOverrides(length, false);
-                break;
-        };
+        }
 
         auto pattern = this->getCommandPattern(cmd);
         length = this->getPattern(cmd.type).size() / commandBus.get_width();
@@ -361,7 +357,7 @@ namespace DRAMPower {
         // Required for precharge power-down
     }
 
-    void DDR4::handleRead(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void DDR4::handleRead(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.reads;
     }
 
@@ -379,7 +375,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR4::handleWrite(Rank &rank, Bank &bank, timestamp_t timestamp) {
+    void DDR4::handleWrite(Rank&, Bank &bank, timestamp_t) {
         ++bank.counter.writes;
     }
 
@@ -493,7 +489,7 @@ namespace DRAMPower {
         });
     }
 
-    void DDR4::endOfSimulation(timestamp_t timestamp) {
+    void DDR4::endOfSimulation(timestamp_t) {
         assert(this->implicitCommandCount() == 0);
 	}